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322 Коммитов

Автор SHA1 Сообщение Дата
Nathan Hjelm
3ff34af355 opal: rename opal_atomic_cmpset* to opal_atomic_bool_cmpset*
This commit renames the atomic compare-and-swap functions to indicate
the return value. This is in preperation for adding support for a
compare-and-swap that returns the old value. At the same time the
return type has been changed to bool.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-10-31 12:47:23 -06:00
Nathan Hjelm
055f413d1b opal/asm: add support for and, or, and xor atomics
This commit adds additional atomics math operations that are needed
throughout the codebase. The semantics of the new operations are
consistent with the existing atomics (op then fetch).

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-10-31 11:39:50 -06:00
Nathan Hjelm
1c52d9dffe opal/asm: clean up no longer supported architectures
We no longer officially support MIPS or ARM before v6. This commit
updates the configury to check for sync builtins on these
architectures and removes the MIPS and IA64 assembly from
opal/include/opal/sys.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-10-11 13:09:29 -06:00
Brian Barrett
5602d3b9c2 atomics: Remove cmpset_64 on IA32
The recent changes to remove non-inline atomics have caused
a cascade of issues with cmpset_64 on IA32.  cmpxchg8 requires
the use of a bunch of registers (2 for every operand, 3 operands),
and one of them is ebx, which is used by the compiler to do
shared library things.  Some compilers don't deal well with
ebx being clobbered (I'm looking at you, gcc 4.1).  Rather than
continue trying to fight, remove cmpset_64 from the supported
atomic operations on IA32.  Other 32 bit platforms (MIPS32,
SPARC32, ARM, etc.) already don't support a 64 bit compare-and-
swap, so while this might slightly reduce performance, it will
at least be correct.

Signed-off-by: Brian Barrett <bbarrett@amazon.com>
2017-09-07 12:19:34 -07:00
George Bosilca
4db3730a25
Be consistent for atomic operations and add an entity
of the same type.

Signed-off-by: George Bosilca <bosilca@icl.utk.edu>
2017-09-01 18:52:48 -04:00
Nathan Hjelm
79fc9d54dc Revert "* Some recent versions of GCC try very hard to make it impossible to"
This reverts commit b5ea5e0994

This commit reverts a change that is hopefully not necessary. If this
is the case this will fix #4146.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-09-01 08:47:29 -06:00
Nathan Hjelm
76320a8ba5 opal: rename opal_atomic_init to opal_atomic_lock_init
This function is used to initalize and opal atomic lock. The old name
was confusing.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-08-07 14:15:11 -06:00
Nathan Hjelm
ebce88b7ad opal: remove generated asm code
Every modern compiler supports either inline assembly or builtin atomic
operations. Because of this it is time to delete all the code associated
with pre-built atomics.

This commit also clean out the DEC and XLC asm checks. Neither check
does anything and the XLC compiler supports GCC ASM.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-08-03 09:18:58 -06:00
Joshua Hursey
4796193cdb atomics/powerpc: Fix WMB instruction
* `lwsync` is a write memory barrier.
    - `eieio` is really not meant for this type of operation.
 * `lwsync` can also be used for the read memory barrier according to
   my reading of the of the Power 8 ISA docs (v2.07)
    - https://www-01.ibm.com/marketing/iwm/iwm/web/reg/download.do?source=swg-opower&S_PKG=dl&lang=en_US&cp=UTF-8
 * References https://github.com/pmix/pmix/pull/391

Signed-off-by: Joshua Hursey <jhursey@us.ibm.com>
2017-06-06 16:41:37 -05:00
Ralph Castain
ef0e0171c9 Implement the changes required to support cross-library coordination. Update PMIx to support intra-process notifications and ensure that we always notify ourselves for events. Add a new ompi/interlib directory where cross-lib coordination code can go, and put the code to declare ourselves there (called from ompi_mpi_init.c).
Signed-off-by: Ralph Castain <rhc@open-mpi.org>
2017-05-08 10:04:50 -07:00
Nicolas Morey-Chaisemartin
b4d9d5ee0f opal: add support for s390 and s390x architectures
Signed-off-by: Nicolas Morey-Chaisemartin <NMoreyChaisemartin@suse.com>
2017-05-05 17:23:42 +02:00
Gilles Gouaillardet
cc8a655fe6 configury: remove now obsolete reference to OPAL_PTRDIFF_TYPE
since Open MPI now requires a C99, and ptrdiff_t type is part of C99,
there is no more need for the abstract OPAL_PTRDIFF_TYPE type.

Thanks George, Nathan and Paul for the help.

Signed-off-by: Gilles Gouaillardet <gilles@rist.or.jp>
2017-04-19 13:42:45 +09:00
Ralph Castain
d645557fa0 Update to include the PMIx 2.0 APIs for monitoring and job control. Include required integration, but leave the monitors off for now. Move the sensor framework out of ORTE as it is being absorbed into PMIx
Fix typo and silence warnings

Signed-off-by: Ralph Castain <rhc@open-mpi.org>
2017-03-21 17:47:08 -07:00
Howard Pritchard
db2e1298fb OSx: remove built-in atomics support
It was decided to remove support for os-x builtin atomics

Fixes #2668

Signed-off-by: Howard Pritchard <howardp@lanl.gov>
2017-03-15 12:45:33 -06:00
Gilles Gouaillardet
af0b5cffb4 asm: rename the AMD64 into X86_64
in this context, AMD64 really means amd64 or em64t, so let's
rename this into X86_64 in order to avoid any confusion

Signed-off-by: Gilles Gouaillardet <gilles@rist.or.jp>
2017-02-27 15:10:50 +09:00
Gilles Gouaillardet
4184c01be5 Merge pull request #2393 from bosilca/topic/no_predefined_ddt_refcount
Don't refcount the predefined datatypes.
2017-02-21 09:38:11 +09:00
Carlos Bederián
ccea3de44c amd64 timers: use lfence instead of cpuid for serialization
Signed-off-by: Carlos Bederián <bc@famaf.unc.edu.ar>
2017-02-04 18:50:29 -03:00
George Bosilca
c2cd717f82 Don't refcount the predefined datatypes.
Signed-off-by: George Bosilca <bosilca@icl.utk.edu>
2017-01-11 16:48:59 -05:00
Nysal Jan K.A
97801028ba asm/ppc: Fix a regression in powerpc atomics
Add a missing constraint to the input operand list.
This fixes a regression caused by d4be138a7b.
Thanks to Orion Poplawski for reporting the issue.

Refs #2610

Signed-off-by: Nysal Jan K.A <jnysal@in.ibm.com>
2017-01-11 11:00:11 -05:00
Nathan Hjelm
5b70ae3ec0 amd64: save/restore all 64 bits of rbx around cpuid
This commit fixes a bug in the timer check. When -fPIC is used we need
to save/restore ebx. The code copied from patcher was meant for 32-bit
systems and did not work correctly on 64-bit systems. This commit
updates the save/restore to use rbx instead of ebx.

Fixes #2678

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2017-01-06 18:54:20 -07:00
Nathan Hjelm
a718743a5c opal/timer: add code to check if rtdtsc is core invariant
Newer x86 processors have a core invariant tsc. On these systems it is
safe to use the rtdtsc instruction as a monotonic timer. This commit
adds a new function to the opal timer code to check if the timer
backend is monotonic. On x86 it checks the appropriate bit and on
other architectures it parrots back the OPAL_TIMER_MONOTONIC value.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-12-16 15:11:50 -07:00
Nathan Hjelm
9a50ce6364 asm/arm64: ensure instruction ordering on timer
Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-10-12 09:25:21 -06:00
Nathan Hjelm
2edc77b27b asm/ppc: work around apparent PGI 16.9 bug
The add_64, sub_64, and cmpset_64 atomics used "+m" (*addr) to
indicate the asm also writes the memory location. This is better than
using a memory clobber. PGI 16.9 introduced a bug that causes a
compiler failure on the "+m" constraint (input/output). It seems to
work with "=m" (output) which matches the 32-bit atomics.

Fixes open-mpi/ompi#2086

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-09-15 12:43:31 -06:00
Nathan Hjelm
27a2509fec Merge pull request #2051 from hjelmn/ppc_asm
opal/asm: updates to powerpc assembly
2016-09-06 15:13:28 -06:00
Gilles Gouaillardet
894be7860a gcc_builtin/atomic: Silence numerous warnings from Studio compilers
This commit adds selective use of a compiler-specific pragma to
silence the numerous warnings the Sun/Oracle/Studio compilers emit for
the GNU-style inline asm used in atomic.h.

Thanks Paul Hargrove for the initial patch and the guidance.
2016-09-06 09:07:16 +09:00
Nathan Hjelm
a36bdfe69f opal/asm: updates to powerpc assembly
This commit contains the following changes:

 - There is a bug in the PGI 16.x betas for ppc64 that causes them to
   emit the incorrect instruction for loading 64-bit operands. If not
   cast to void * the operands are loaded with lwz (load word and
   zero) instead of ld. This does not affect optimized mode. The work
   around is to cast to void * and was implemented similar to a
   work-around for a xlc bug.

 - Actually implement 64-bit add/sub. These functions were missing and
   fell back to the less efficient compare-and-swap implementations.

Thanks to @PHHargrove for helping to track this down. With this update
the GCC inline assembly works as expected with pgi and ppc64.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-09-02 23:47:47 -06:00
Ralph Castain
0ea1cff733 Implement notification of completion on comm_spawn'd child jobs. Add a configure flag to enable PMIx 3's shared memory datastore, and set it disable by default so that comm_spawn functions again. Will reverse the default once that feature is fully functional 2016-09-01 13:10:10 -07:00
George Bosilca
a6d515ba9e Fixes opal_atomic_ll_64. Thanks to Paul Hardgrove for
the report and his patch.

This is an addition to #1140 and should go in 2.x
2016-08-27 12:43:48 -04:00
Gilles Gouaillardet
1778e5b586 atomic/sparcv9: fix a typo in the comment, no code change 2016-08-01 10:34:02 +09:00
Gilles Gouaillardet
273e56096b configury: capture configury command line
configury command line is quoted and made available via the OPAL_CONFIGURE_CLI macro.
it can be retrieved via {orte-info,ompi_info,oshmem_info} -c, or
{orte-info,ompi_info,oshmem_info} --all --parseable | grep ^config:cli:
2016-07-29 09:14:09 +09:00
Ralph Castain
20a91c2baf Add a new --continuous flag to mpirun that directs ORTE to let a job continue running as app procs terminate. Don't attempt to restart them. Add event notification of abnormally terminating procs, and demonstrate that in the mpi_spin test program.
Cleanup debug message
2016-07-13 15:28:33 -07:00
Ralph Castain
6e434d6785 Add support for PMIx tool connections and queries. Initially only support a request to list all known namespaces (jobids) from ORTE, but other folks will extend that support to include additional information
Update to match PMIx RFC

Fix configury to point to correct libevent and hwloc locations
2016-06-29 19:19:19 -07:00
Abhishek Joshi
f06f7eb3e6 arm64: add timer support
Signed-off-by: Sreenidhi Bharathkar Ramesh <sreenidhi-bharathkar.ramesh@broadcom.com>
2016-06-23 11:01:00 +00:00
Nathan Hjelm
2e4141f20a Merge pull request #1787 from hjelmn/asm_fix
opal/asm: fix syntax of timer code for ia32
2016-06-17 08:50:57 -06:00
Nathan Hjelm
9c709966f7 opal/asm: fix syntax of timer code for ia32
Thanks to Paul Hargrove for pointing this out.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-06-16 16:55:01 -06:00
Ralph Castain
5d330d5220 Enable the PMIx event notification capability and use that for all error notifications, including debugger release. This capability requires use of PMIx 2.0 or above as the features are not available with earlier PMIx releases. When OMPI master is built against an earlier external version, it will fallback to the prior behavior - i.e., debugger will be released via RML and all notifications will go strictly to the default error handler.
Add PMIx 2.0

Remove PMIx 1.1.4

Cleanup copying of component

Add missing file

Touchup a typo in the Makefile.am

Update the pmix ext114 component

Minor cleanups and resync to master

Update to latest PMIx 2.x

Update to the PMIx event notification branch latest changes
2016-06-14 13:08:41 -07:00
Nathan Hjelm
253c91972e arm64: add atomic swap function
This commit adds the opal_atomic_swap_32 and opal_atomic_swap_64
functions. This should improve the performance of btl/vader.

Signed-off-by: Nathan Hjelm <hjelmn@me.com>
2016-06-11 09:46:29 -06:00
Nathan Hjelm
109389dce2 Merge pull request #1634 from hjelmn/cma
cma: add support for MIPS and ARM
2016-06-11 09:20:28 -06:00
Nathan Hjelm
4a2bd83302 opal/cma: improve Linux CMA detection
This commit improves the CMA detection when the installed glibc doesn't
have support for CMA. In this case we need to verify that the syscall
numbers in opal/include/opal/sys/cma.h are valid for the architecture.
This verification is done by attempting to use CMA while including the
internal header.

Signed-off-by: Nathan Hjelm <hjelmn@me.com>
2016-06-05 22:29:07 -06:00
Nathan Hjelm
0084ad0d1b opal: add armv8 support
This commit adds assembly support for aarch64.

Signed-off-by: Nathan Hjelm <hjelmn@me.com>
2016-06-03 10:32:21 -06:00
Nathan Hjelm
d9fc855955 Merge pull request #1743 from hjelmn/gcc_atomics_fix
atomic/gcc: add check for 128-bit CAS being lock-free
2016-06-02 16:55:31 -06:00
Nathan Hjelm
d86e41ea13 atomic/gcc: add check for 128-bit CAS being lock-free
Compiler implementations are free to include support for atomics that
use locks. Unfortunately lock-free and lock atomics do not mix. Older
versions of llvm on OS X use locks to provide
__atomic_compare_exchange on 128-bit values but are lock-free on
64-bit values. This screws up our lifo implementation which mixes
64-bit and 128-bit atomics on the same values to improve
performance. This commit adds a configure-time check if 128-bit
atomics are lock free. If they are not then the 128-bit __atomic CAS
is disabled and we check for the __sync version as a fallback.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-06-02 15:59:05 -06:00
Nathan Hjelm
5aab4b2d51 Merge pull request #1662 from ggouaillardet/topic/amd64_atomic
amd64/atomic: silence warnings
2016-06-02 14:10:20 -06:00
Nathan Hjelm
f33bbfd381 atomic: add support for __atomic builtins (#1735)
* atomic: add support for __atomic builtins

This commit adds support for the gcc __atomic builtins. The __sync
builtins are deprecated and have been replaced by these atomics. In
addition, the new atomics support atomic exchange which was not
supported by __sync.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>

* atomic: add support for transactional memory

This commit adds support for using transactional memory when using
opal atomic locks. This feature is enabled if the __HLE__ feature is
available and the gcc builtin atomics are in use.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-06-01 21:23:47 -04:00
Nathan Hjelm
60519c2b4e cma: add support for MIPS and ARM
Signed-off-by: Nathan Hjelm <hjelmn@me.com>
2016-05-30 12:13:20 -06:00
Gilles Gouaillardet
5dae7a47ff amd64/atomic: silence warnings
Solaris Studio compilers issue (tons of) warnings because one arguments of several __asm__ __volatile__ section is not needed
2016-05-11 11:26:50 +09:00
Nathan Hjelm
d99a9786b6 sync_builtin: check for 64-bit atomic support
This commit adds an additional check for 64-bit atomic support for __sync
builtins. If 64-bit support is not available the opal_atomic_*_64 atomics
are disabled.

Signed-off-by: Nathan Hjelm <hjelmn@me.com>
2016-05-09 03:17:51 -06:00
Joshua Hursey
788cf1a9fe asm/powerpc: Fix empty colon list in asm for XL compiler on power
Thanks to Paul Hargrove for reporting the problem, and submitting patch.
 * https://www.open-mpi.org/community/lists/devel/2016/05/18886.php
2016-05-04 14:14:33 -05:00
Karol Mroz
e1c64e6e59 opal: standardize on max hostname length
Define OPAL_MAXHOSTNAMELEN to be either:
  (MAXHOSTNAMELEN + 1) or
  (limits.h:HOST_NAME_MAX + 1) or
  (255 + 1)

For pmix code, define above using PMIX_MAXHOSTNAMELEN.

Fixup opal layer to use the new max.

Signed-off-by: Karol Mroz <mroz.karol@gmail.com>
2016-04-24 08:19:47 +02:00
Nathan Hjelm
d4afb16f5a opal: rework mpool and rcache frameworks
This commit rewrites both the mpool and rcache frameworks. Summary of
changes:

 - Before this change a significant portion of the rcache
   functionality lived in mpool components. This meant that it was
   impossible to add a new memory pool to use with rdma networks
   (ugni, openib, etc) without duplicating the functionality of an
   existing mpool component. All the registration functionality has
   been removed from the mpool and placed in the rcache framework.

 - All registration cache mpools components (udreg, grdma, gpusm,
   rgpusm) have been changed to rcache components. rcaches are
   allocated and released in the same way mpool components were.

 - It is now valid to pass NULL as the resources argument when
   creating an rcache. At this time the gpusm and rgpusm components
   support this. All other rcache components require non-NULL
   resources.

 - A new mpool component has been added: hugepage. This component
   supports huge page allocations on linux.

 - Memory pools are now allocated using "hints". Each mpool component
   is queried with the hints and returns a priority. The current hints
   supported are NULL (uses posix_memalign/malloc), page_size=x (huge
   page mpool), and mpool=x.

 - The sm mpool has been moved to common/sm. This reflects that the sm
   mpool is specialized and not meant for any general
   allocations. This mpool may be moved back into the mpool framework
   if there is any objection.

 - The opal_free_list_init arguments have been updated. The unused0
   argument is not used to pass in the registration cache module. The
   mpool registration flags are now rcache registration flags.

 - All components have been updated to make use of the new framework
   interfaces.

As this commit makes significant changes to both the mpool and rcache
frameworks both versions have been bumped to 3.0.0.

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
2016-03-14 10:50:41 -06:00