Merge pull request #2051 from hjelmn/ppc_asm
opal/asm: updates to powerpc assembly
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Коммит
27a2509fec
@ -11,7 +11,7 @@
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* Copyright (c) 2004-2005 The Regents of the University of California.
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* All rights reserved.
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* Copyright (c) 2010 IBM Corporation. All rights reserved.
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* Copyright (c) 2015 Los Alamos National Security, LLC. All rights
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* Copyright (c) 2015-2016 Los Alamos National Security, LLC. All rights
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* reserved.
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* $COPYRIGHT$
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*
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@ -55,6 +55,9 @@
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#define OPAL_HAVE_ATOMIC_CMPSET_64 1
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#define OPAL_HAVE_ATOMIC_SWAP_64 1
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#define OPAL_HAVE_ATOMIC_LLSC_64 1
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#define OPAL_HAVE_ATOMIC_MATH_64 1
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#define OPAL_HAVE_ATOMIC_ADD_64 1
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#define OPAL_HAVE_ATOMIC_SUB_64 1
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#endif
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@ -128,6 +131,16 @@ void opal_atomic_isync(void)
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#define OPAL_ASM_ADDR(a) (a)
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#endif
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#if defined(__PGI)
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/* work-around for bug in PGI 16.5-16.7 where the compiler fails to
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* correctly emit load instructions for 64-bit operands. without this
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* it will emit lwz instead of ld to load the 64-bit operand. */
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#define OPAL_ASM_VALUE64(x) (void *)(intptr_t) (x)
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#else
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#define OPAL_ASM_VALUE64(x) x
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#endif
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static inline int opal_atomic_cmpset_32(volatile int32_t *addr,
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int32_t oldval, int32_t newval)
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{
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@ -217,6 +230,38 @@ static inline int32_t opal_atomic_swap_32(volatile int32_t *addr, int32_t newval
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#if (OPAL_ASSEMBLY_ARCH == OPAL_POWERPC64)
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#if OPAL_GCC_INLINE_ASSEMBLY
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static inline int64_t opal_atomic_add_64 (volatile int64_t* v, int64_t inc)
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{
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int64_t t;
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__asm__ __volatile__("1: ldarx %0, 0, %3 \n\t"
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" add %0, %2, %0 \n\t"
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" stdcx. %0, 0, %3 \n\t"
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" bne- 1b \n\t"
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: "=&r" (t), "+m" (*v)
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: "r" (OPAL_ASM_VALUE64(inc)), "r" OPAL_ASM_ADDR(v)
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: "cc");
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return t;
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}
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static inline int64_t opal_atomic_sub_64 (volatile int64_t* v, int64_t dec)
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{
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int64_t t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 \n\t"
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" subf %0,%2,%0 \n\t"
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" stdcx. %0,0,%3 \n\t"
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" bne- 1b \n\t"
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: "=&r" (t), "+m" (*v)
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: "r" (OPAL_ASM_VALUE64(dec)), "r" OPAL_ASM_ADDR(v)
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: "cc");
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return t;
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}
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static inline int opal_atomic_cmpset_64(volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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@ -229,8 +274,8 @@ static inline int opal_atomic_cmpset_64(volatile int64_t *addr,
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" stdcx. %4, 0, %2 \n\t"
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" bne- 1b \n\t"
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"2:"
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: "=&r" (ret), "=m" (*addr)
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: "r" (addr), "r" (oldval), "r" (newval), "m" (*addr)
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: "=&r" (ret), "+m" (*addr)
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: "r" (addr), "r" (OPAL_ASM_VALUE64(oldval)), "r" (OPAL_ASM_VALUE64(newval))
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: "cc", "memory");
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return (ret == oldval);
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@ -249,15 +294,15 @@ static inline int64_t opal_atomic_ll_64(volatile int64_t *addr)
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static inline int opal_atomic_sc_64(volatile int64_t *addr, int64_t newval)
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{
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int32_t ret, foo;
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int32_t ret;
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__asm__ __volatile__ (" stdcx. %4, 0, %3 \n\t"
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__asm__ __volatile__ (" stdcx. %2, 0, %1 \n\t"
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" li %0,0 \n\t"
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" bne- 1f \n\t"
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" ori %0,%0,1 \n\t"
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"1:"
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: "=r" (ret), "=m" (*addr), "=r" (foo)
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: "r" (addr), "r" (newval)
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: "=r" (ret)
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: "r" (addr), "r" (OPAL_ASM_VALUE64(newval))
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: "cc", "memory");
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return ret;
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}
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@ -294,7 +339,7 @@ static inline int64_t opal_atomic_swap_64(volatile int64_t *addr, int64_t newval
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" stdcx. %3, 0, %2 \n\t"
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" bne- 1b \n\t"
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: "=&r" (ret), "=m" (*addr)
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: "r" (addr), "r" (newval)
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: "r" (addr), "r" (OPAL_ASM_VALUE64(newval))
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: "cc", "memory");
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return ret;
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