since the 1.4 release (and configure would abort when run with sparc v8), but
the code was left in place. Sparc v9 (32 or 64 bit) are still supported
targets.
This commit was SVN r25258.
* The opal_sys_timer_get_cycles() call was implemented for
Sparc v9 using inline assembly, but not in the assembly files.
This would only currently matter on Linux Sparc systems using
a compiler that didn't support inline assembly (not many of
those), but it should be there for completion.
* The linux timer component would always build on non-Alpha
platforms, rather than only building on platforms where
opal_sys_timer_get_cycles() was implemented. This would
only matter on a very narrow set of platforms that we don't
really support, but still, it could be more right. We now
only build the component on platforms where we have the
assembly call to get the cycle counter.
* Added a comment to opal/sys/timer.h to note that the linux
timer component needed to be updated if another platform was
added.
This should be harmless to commit. It will only really change
behaviors on platforms we don't have assembly support for, which
currently won't make it through configure. It really only matters
when (if?) we support atomic operations through libatomic_ops.
This commit was SVN r17887.
there is an exit path out of the loop
* Reformat assembly to match other platforms
* Update base file for non-inline assembly to match changes in
the inline version
This commit was SVN r11803.
* Use $31 instead of mnemonic zero for the gcc inline
assembly test, as the GNU assembler doesn't like
zero, but both Tru64 and GNU assembler should be fine
with $31
* Disable Linux timer component on Alpha. The CPU timer
rolls over every 10 seconds or less, so it's kinda
worthless for our needs.
* Fix some escaping issues when local functions are
denoted with a $
* Remove C++ comments from the Alpha assembly.
* Add base assembly code for the non-inlined functions
on Alpha
This commit was SVN r11764.
need memory barriers to actually do something other than hint
to the compiler not to reorder memory-related instructions. The
IA64 instruction for memory barriers is "mf".
Fixes bug #137.
This commit was SVN r10401.
as I understand how that one works and don't really understand what
was in the amd64 code (which was copied from before I started working
on the inline assembly). This fixes the race condition we were
seeing on PGI causing test failures
* sync non-inline assembly with inline assembly version
This needs to go to the v1.0 branch
This commit was SVN r9539.
