Pushing the Debian patch (based on Manuel Prinz modifications).

This commit was SVN r24061.

opal/asm/asm-data.txt

@@ -127,3 +127,7 @@ SPARCV9_64	default-.text-.globl-:--.L-#-1-0-1-1-0	sparcv9-64-solaris
 
 MIPS	default-.text-.globl-:--L--1-1-1-1-0	mips-irix
 MIPS	default-.text-.globl-:--L--1-1-1-1-0	mips64el
+MIPS	default-.text-.globl-:--L-@-1-1-1-1-1	mips64-linux
+
+# However, this doesn't hold true for 32-bit MIPS as used on Linux.
+MIPS	default-.text-.globl-:--L-@-1-1-1-0-1	mips-linux

opal/asm/base/MIPS.asm

@@ -1,26 +1,48 @@
 START_FILE
 
+#ifdef __linux__
 #include <sys/asm.h>
+#else
+#include <asm.h>
+#endif
 #include <regdef.h>
 	
 	TEXT
 
 	ALIGN(8)
 LEAF(opal_atomic_mb)
+#ifdef __linux__
+	.set mips2
+#endif
 	sync
+#ifdef __linux__
+	.set mips0
+#endif	
 	j	ra
 END(opal_atomic_mb)
 
 	
 	ALIGN(8)
 LEAF(opal_atomic_rmb)
+#ifdef __linux__
+	.set mips2
+#endif
 	sync
+#ifdef __linux__
+	.set mips0
+#endif
 	j	ra
 END(opal_atomic_rmb)
 	
 	
 LEAF(opal_atomic_wmb)
+#ifdef __linux__
+	.set mips2
+#endif
 	sync
+#ifdef __linux__
+	.set mips0
+#endif
 	j	ra
 END(opal_atomic_wmb)
 
@@ -28,7 +50,13 @@ END(opal_atomic_wmb)
 LEAF(opal_atomic_cmpset_32)
 	.set noreorder        
 retry1:                
+#ifdef __linux__
+	.set mips2
+#endif
 	ll     $3, 0($4)         
+#ifdef __linux__
+	.set mips0
+#endif
 	bne    $3, $5, done1   
 	or     $2, $6, 0      
 	sc     $2, 0($4)         
@@ -45,13 +73,31 @@ END(opal_atomic_cmpset_32)
 LEAF(opal_atomic_cmpset_acq_32)
 	.set noreorder        
 retry2:                
+#ifdef __linux__
+	.set mips2
+#endif
 	ll     $3, 0($4)         
+#ifdef __linux__
+	.set mips0
+#endif
 	bne    $3, $5, done2   
 	or     $2, $6, 0      
+#ifdef __linux__
+	.set mips2
+#endif
 	sc     $2, 0($4)         
+#ifdef __linux__
+	.set mips0
+#endif
 	beqz   $2, retry2   
 done2:                 
+#ifdef __linux__
+	.set mips2
+#endif
 	sync
+#ifdef __linux__
+	.set mips0
+#endif
 	.set reorder          
 
 	xor	$3,$3,$5
@@ -62,12 +108,30 @@ END(opal_atomic_cmpset_acq_32)
 	
 LEAF(opal_atomic_cmpset_rel_32)
 	.set noreorder        
+#ifdef __linux__
+	.set mips2
+#endif
 	sync
+#ifdef __linux__
+	.set mips0
+#endif
 retry3:                
+#ifdef __linux__
+	.set mips2
+#endif
 	ll     $3, 0($4)         
+#ifdef __linux__
+	.set mips0
+#endif
 	bne    $3, $5, done3   
 	or     $2, $6, 0      
+#ifdef __linux__
+	.set mips2
+#endif
 	sc     $2, 0($4)         
+#ifdef __linux__
+	.set mips0
+#endif
 	beqz   $2, retry3   
 done3:                 
 	.set reorder          
@@ -77,7 +141,7 @@ done3:
 	sltu	$2,$3,1
 END(opal_atomic_cmpset_rel_32)
 	
-	
+#ifdef __mips64	
 LEAF(opal_atomic_cmpset_64)
 		.set noreorder        
 retry4:                
@@ -128,3 +192,4 @@ done6:
 	j	ra
 	sltu	$3,$4,1
 END(opal_atomic_cmpset_rel_64)
+#endif /* __mips64 */

opal/include/opal/sys/mips/atomic.h

@@ -23,10 +23,17 @@
 #if OPAL_WANT_SMP_LOCKS
 
 /* BWB - FIX ME! */
+#ifdef __linux__
+#define MB() __asm__ __volatile__(".set mips2; sync; .set mips0": : :"memory")
+#define RMB() __asm__ __volatile__(".set mips2; sync; .set mips0": : :"memory")
+#define WMB() __asm__ __volatile__(".set mips2; sync; .set mips0": : :"memory")
+#define SMP_SYNC ".set mips2; sync; .set mips0"
+#else
 #define MB() __asm__ __volatile__("sync": : :"memory")
 #define RMB() __asm__ __volatile__("sync": : :"memory")
 #define WMB() __asm__ __volatile__("sync": : :"memory")
 #define SMP_SYNC "sync"
+#endif
 
 #else
 
@@ -46,8 +53,10 @@
 #define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
 
 #define OPAL_HAVE_ATOMIC_CMPSET_32 1
-#define OPAL_HAVE_ATOMIC_CMPSET_64 1
 
+#ifdef __mips64
+#define OPAL_HAVE_ATOMIC_CMPSET_64 1
+#endif
 
 /**********************************************************************
  *
@@ -93,10 +102,16 @@ static inline int opal_atomic_cmpset_32(volatile int32_t *addr,
    __asm__ __volatile__ (".set noreorder        \n"
                          ".set noat             \n"
                          "1:                    \n"
+#ifdef __linux__
+                         ".set mips2         \n\t"
+#endif
                          "ll     %0, %2         \n" /* load *addr into ret */
                          "bne    %0, %z3, 2f    \n" /* done if oldval != ret */
                          "or     $1, %z4, 0     \n" /* tmp = newval (delay slot) */
                          "sc     $1, %2         \n" /* store tmp in *addr */
+#ifdef __linux__
+                         ".set mips0         \n\t"
+#endif
                          /* note: ret will be 0 if failed, 1 if succeeded */
                          "beqz   $1, 1b         \n" /* if 0 jump back to 1b */
 			 "nop                   \n" /* fill delay slots */
@@ -133,7 +148,7 @@ static inline int opal_atomic_cmpset_rel_32(volatile int32_t *addr,
     return opal_atomic_cmpset_32(addr, oldval, newval);
 }
 
-
+#ifdef OPAL_HAVE_ATOMIC_CMPSET_64
 static inline int opal_atomic_cmpset_64(volatile int64_t *addr,
                                         int64_t oldval, int64_t newval)
 {
@@ -182,6 +197,7 @@ static inline int opal_atomic_cmpset_rel_64(volatile int64_t *addr,
     opal_atomic_wmb();
     return opal_atomic_cmpset_64(addr, oldval, newval);
 }
+#endif /* OPAL_HAVE_ATOMIC_CMPSET_64 */
 
 #endif /* OMPI_GCC_INLINE_ASSEMBLY */