Brian Barrett 01913be4e6 * IA64 can have a weaker consistency model for memory than x86, so we ... need memory barriers to actually do something other than hint to the compiler not to reorder memory-related instructions. The IA64 instruction for memory barriers is "mf". Fixes bug #137. This commit was SVN r10401.		2006-06-17 05:01:54 +00:00
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aix.conf	Initial population of the opal tree	2005-07-02 13:43:20 +00:00
AMD64.asm	* sync opal_atomic_cmpset_{32,64} for AMD64 with the x86 32 bit version,	2006-04-06 01:23:33 +00:00
default.conf	Initial population of the opal tree	2005-07-02 13:43:20 +00:00
IA32.asm	- Delete the compiler-generated comments APP/NO_APP, as some	2006-03-16 15:14:00 +00:00
IA64.asm	* IA64 can have a weaker consistency model for memory than x86, so we	2006-06-17 05:01:54 +00:00
MIPS.asm	- Delete the compiler-generated comments APP/NO_APP, as some	2006-03-16 15:14:00 +00:00
POWERPC32.asm	* support high-res timers even if we don't have inline assembly	2005-08-23 21:50:23 +00:00
POWERPC64.asm	* fix duplicate local symbol probelm in PPC64 assembly	2005-08-25 16:37:48 +00:00
SPARC.asm	* rename all the atomic functions from ompi to opal	2005-07-03 21:38:51 +00:00
SPARCV9_32.asm	* rename all the atomic functions from ompi to opal	2005-07-03 21:38:51 +00:00
SPARCV9_64.asm	* rename all the atomic functions from ompi to opal	2005-07-03 21:38:51 +00:00