551c2ea480
This commit removes alpha asm support. No current processor manufacturer makes chips compatible with DEC alpha and no participating organization has alpha processors. This makes it difficult to support alpha via assembly. This doesn't mean Open MPI will no longer build/work on alpha processors. It should continue to work with gcc's builtin sync atomics. Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
132 строки
4.9 KiB
Bash
132 строки
4.9 KiB
Bash
# -*- sh -*-
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# Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
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# University Research and Technology
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# Corporation. All rights reserved.
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# Copyright (c) 2004-2005 The University of Tennessee and The University
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# of Tennessee Research Foundation. All rights
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# reserved.
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# Copyright (c) 2004-2005 High Performance Computing Center Stuttgart,
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# University of Stuttgart. All rights reserved.
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# Copyright (c) 2004-2005 The Regents of the University of California.
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# All rights reserved.
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# Copyright (c) 2014 Intel, Inc. All rights reserved.
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# $COPYRIGHT$
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#
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# Additional copyrights may follow
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#
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# $HEADER$
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#
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#
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# Database for mapping architecture and assembly format to prebuilt
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# assembly files. For explination of the assembly operations, see
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# the inline assembly header files in src/include/sys/<arch>.
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#
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# FORMAT:
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# ARCHITECTURE ASSEMBLY FORMAT BASE FILENAME
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#
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# Assembly Format field:
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# config_file-text-global-label_suffix-gsym-lsym-type-size-align_log-ppc_r_reg-64_bit-gnu_stack
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######################################################################
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#
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# AMD Opteron / Intel EM64T
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#
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######################################################################
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AMD64 default-.text-.globl-:--.L-@-1-0-1-1-1 amd64-linux
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AMD64 default-.text-.globl-:--.L-@-1-0-1-1-0 amd64-linux-nongas
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######################################################################
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#
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# ARM (ARMv7 and later)
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#
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######################################################################
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ARM default-.text-.globl-:--.L-#-1-1-1-1-1 arm-linux
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######################################################################
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#
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# Intel Pentium Class
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#
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######################################################################
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IA32 default-.text-.globl-:--.L-@-1-0-1-1-1 ia32-linux
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IA32 default-.text-.globl-:--.L-@-1-0-1-1-0 ia32-linux-nongas
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IA32 default-.text-.globl-:-_-L--0-1-1-1-0 ia32-osx
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IA32 default-.text-.globl-:-_-L--0-0-1-1-1 ia32-cygwin
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IA32 default-.text-.globl-:-_-L--0-0-1-1-0 ia32-cygwin-nongas
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######################################################################
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#
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# IA64 (Intel Itanium)
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#
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######################################################################
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IA64 default-.text-.globl-:--.L-@-1-0-1-1-1 ia64-linux
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IA64 default-.text-.globl-:--.L-@-1-0-1-1-0 ia64-linux-nongas
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######################################################################
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#
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# PowerPC / POWER
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#
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######################################################################
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# standard ppc instruction set (AIX calls it ppc). This is not the
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# true intersection of all the POWER / PowerPC machines, but works
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# on PowerPCs since the 601 and on at least POWER 3 and above.
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POWERPC32 default-.text-.globl-:-_-L--0-1-1-0-0 powerpc32-osx
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POWERPC32 default-.text-.globl-:--.L-@-1-1-0-0-1 powerpc32-linux
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POWERPC32 default-.text-.globl-:--.L-@-1-1-0-0-0 powerpc32-linux-nongas
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POWERPC32 aix-.csect .text[PR]-.globl-:-.-L--0-1-0-0-0 powerpc32-aix
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# The ppc code above, plus support for the 64 bit operations. This
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# mode is really only available on OS X when using the OS X 10.3
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# compiler chain with the -mcpu=970 option.
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POWERPC32 default-.text-.globl-:-_-L--0-1-1-1-0 powerpc32-64-osx
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# PowerPC / POWER 64bit machines. sizeof(void*) == 8.
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POWERPC64 default-.text-.globl-:-_-L--0-1-1-1-0 powerpc64-osx
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POWERPC64 default-.text-.globl-:-.-.L-@-1-1-0-1-1 powerpc64-linux
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POWERPC64 default-.text-.globl-:-.-.L-@-1-1-0-1-0 powerpc64-linux-nongas
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POWERPC64 aix-.csect .text[PR]-.globl-:-.-L--0-1-0-1-0 powerpc64-aix
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######################################################################
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#
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# SPARC / UltraSPARC (Scalalable Processor ARChitecture)
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#
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######################################################################
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# Usually compiled with -xarch=v8plus. Basically Sparc V9, but with
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# sizeof(void*) == 4 instead of 8. Different from V9_64 because still
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# uses 2 registers to pass in a 64bit integer
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SPARCV9_32 default-.text-.globl-:--.L-#-1-0-1-1-0 sparcv9-32-solaris
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# The Sparc v9 (aka Ultra Sparc). Sizeof(void*) == 8.
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SPARCV9_64 default-.text-.globl-:--.L-#-1-0-1-1-0 sparcv9-64-solaris
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######################################################################
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#
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# MIPS III (Microprocessor without Interlocked Pipeline Stages)
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# R4000 and above
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#
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######################################################################
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# So MIPS, in it's infinite wisdom (thank you!) decided that when
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# compiling in 32bit mode and passing in a 64bit integer, it is done
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# in one register (instead of SPARC and POWER, who use two). Which
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# means that we can use the same code either way. Woo hoo!
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MIPS default-.text-.globl-:--L--1-1-1-1-0 mips-irix
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MIPS default-.text-.globl-:--L--1-1-1-1-0 mips64el
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MIPS default-.text-.globl-:--L-@-1-1-1-1-1 mips64-linux
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# However, this doesn't hold true for 32-bit MIPS as used on Linux.
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MIPS default-.text-.globl-:--L-@-1-1-1-0-1 mips-linux
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