atomic/ppc: add atomics for load-link, store-conditional, and swap
This commit adds implementations of opal_atomic_ll_32/64 and opal_atomic_sc_32/64. These atomics can be used to implement more efficient lifo/fifo operations on supported platforms. The only supported platform with this commit is powerpc/power. This commit also adds an implementation of opal_atomic_swap_32/64 for powerpc. Tested with Power8. Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
Этот коммит содержится в:
Nathan Hjelm
родитель
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Коммит
6a19a10fbb
@ -1,3 +1,4 @@
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/* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil -*- */
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/*
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* Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
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* University Research and Technology
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@ -11,7 +12,7 @@
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* All rights reserved.
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* Copyright (c) 2007 Sun Microsystems, Inc. All rights reserved.
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* Copyright (c) 2011 Sandia National Laboratories. All rights reserved.
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* Copyright (c) 2013-2015 Los Alamos National Security, LLC. All rights
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* Copyright (c) 2011-2015 Los Alamos National Security, LLC. All rights
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* reserved.
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* $COPYRIGHT$
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*
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@ -38,7 +39,7 @@
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* - \c OPAL_HAVE_ATOMIC_MEM_BARRIER atomic memory barriers
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* - \c OPAL_HAVE_ATOMIC_SPINLOCKS atomic spinlocks
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* - \c OPAL_HAVE_ATOMIC_MATH_32 if 32 bit add/sub/cmpset can be done "atomicly"
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* - \c OPAL_HAVE_ATOMIC_MATH_64 if 32 bit add/sub/cmpset can be done "atomicly"
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* - \c OPAL_HAVE_ATOMIC_MATH_64 if 64 bit add/sub/cmpset can be done "atomicly"
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*
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* Note that for the Atomic math, atomic add/sub may be implemented as
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* C code using opal_atomic_cmpset. The appearance of atomic
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@ -177,6 +178,12 @@ typedef struct opal_atomic_lock_t opal_atomic_lock_t;
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#ifndef OPAL_HAVE_ATOMIC_CMPSET_128
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#define OPAL_HAVE_ATOMIC_CMPSET_128 0
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#endif
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#ifndef OPAL_HAVE_ATOMIC_LLSC_32
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#define OPAL_HAVE_ATOMIC_LLSC_32 0
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#endif
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#ifndef OPAL_HAVE_ATOMIC_LLSC_64
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#define OPAL_HAVE_ATOMIC_LLSC_64 0
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#endif
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#endif /* DOXYGEN */
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/**********************************************************************
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@ -11,7 +11,7 @@
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* Copyright (c) 2004-2005 The Regents of the University of California.
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* All rights reserved.
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* Copyright (c) 2010-2014 Cisco Systems, Inc. All rights reserved.
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* Copyright (c) 2012-2014 Los Alamos National Security, LLC. All rights
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* Copyright (c) 2012-2015 Los Alamos National Security, LLC. All rights
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* reserved.
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* $COPYRIGHT$
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*
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@ -274,6 +274,30 @@ static inline int opal_atomic_cmpset_rel_ptr(volatile void* addr,
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#endif /* (OPAL_HAVE_ATOMIC_SWAP_32 || OPAL_HAVE_ATOMIC_SWAP_64) */
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#if (OPAL_HAVE_ATOMIC_LLSC_32 || OPAL_HAVE_ATOMIC_LLSC_64)
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#if SIZEOF_VOID_P == 4 && OPAL_HAVE_ATOMIC_LLSC_32
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#define opal_atomic_ll_ptr(addr) (void *) opal_atomic_ll_32((int32_t *) addr)
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#define opal_atomic_sc_ptr(addr, newval) opal_atomic_sc_32((int32_t *) addr, (int32_t) newval)
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#define OPAL_HAVE_ATOMIC_LLSC_PTR 1
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#elif SIZEOF_VOID_P == 8 && OPAL_HAVE_ATOMIC_LLSC_64
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#define opal_atomic_ll_ptr(addr) (void *) opal_atomic_ll_64((int64_t *) addr)
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#define opal_atomic_sc_ptr(addr, newval) opal_atomic_sc_64((int64_t *) addr, (int64_t) newval)
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#define OPAL_HAVE_ATOMIC_LLSC_PTR 1
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#endif
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#endif /* (OPAL_HAVE_ATOMIC_LLSC_32 || OPAL_HAVE_ATOMIC_LLSC_64)*/
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#if !defined(OPAL_HAVE_ATOMIC_LLSC_PTR)
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#define OPAL_HAVE_ATOMIC_LLSC_PTR 0
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#endif
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#if OPAL_HAVE_ATOMIC_MATH_32 || OPAL_HAVE_ATOMIC_MATH_64
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@ -1,3 +1,4 @@
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/* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil -*- */
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/*
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* Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
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* University Research and Technology
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@ -10,6 +11,8 @@
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* Copyright (c) 2004-2005 The Regents of the University of California.
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* All rights reserved.
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* Copyright (c) 2010 IBM Corporation. All rights reserved.
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* Copyright (c) 2015 Los Alamos National Security, LLC. All rights
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* reserved.
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* $COPYRIGHT$
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*
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* Additional copyrights may follow
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@ -40,6 +43,8 @@
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#define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
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#define OPAL_HAVE_ATOMIC_CMPSET_32 1
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#define OPAL_HAVE_ATOMIC_SWAP_32 1
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#define OPAL_HAVE_ATOMIC_LLSC_32 1
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#define OPAL_HAVE_ATOMIC_MATH_32 1
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#define OPAL_HAVE_ATOMIC_ADD_32 1
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@ -48,6 +53,8 @@
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#if (OPAL_ASSEMBLY_ARCH == OPAL_POWERPC64) || OPAL_ASM_SUPPORT_64BIT
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#define OPAL_HAVE_ATOMIC_CMPSET_64 1
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#define OPAL_HAVE_ATOMIC_SWAP_64 1
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#define OPAL_HAVE_ATOMIC_LLSC_64 1
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#endif
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@ -140,6 +147,32 @@ static inline int opal_atomic_cmpset_32(volatile int32_t *addr,
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return (ret == oldval);
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}
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static inline int32_t opal_atomic_ll_32 (volatile int32_t *addr)
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{
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int32_t ret;
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__asm__ __volatile__ ("lwarx %0, 0, %1 \n\t"
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: "=&r" (ret)
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: "r" (addr)
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:);
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return ret;
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}
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static inline int opal_atomic_sc_32 (volatile int32_t *addr, int32_t newval)
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{
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int32_t ret, foo;
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__asm__ __volatile__ (" stwcx. %4, 0, %3 \n\t"
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" li %0,0 \n\t"
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" bne- 1f \n\t"
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" ori %0,%0,1 \n\t"
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"1:"
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: "=r" (ret), "=m" (*addr), "=r" (foo)
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: "r" (addr), "r" (newval)
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: "cc", "memory");
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return ret;
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}
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/* these two functions aren't inlined in the non-gcc case because then
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there would be two function calls (since neither cmpset_32 nor
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atomic_?mb can be inlined). Instead, we "inline" them by hand in
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@ -164,6 +197,20 @@ static inline int opal_atomic_cmpset_rel_32(volatile int32_t *addr,
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return opal_atomic_cmpset_32(addr, oldval, newval);
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}
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static inline int32_t opal_atomic_swap_32(volatile int32_t *addr, int32_t newval)
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{
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int32_t ret;
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__asm__ __volatile__ ("1: lwarx %0, 0, %2 \n\t"
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" stwcx. %3, 0, %2 \n\t"
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" bne- 1b \n\t"
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: "=&r" (ret), "=m" (*addr)
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: "r" (addr), "r" (newval)
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: "cc", "memory");
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return ret;
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}
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#endif /* OPAL_GCC_INLINE_ASSEMBLY */
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@ -189,6 +236,32 @@ static inline int opal_atomic_cmpset_64(volatile int64_t *addr,
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return (ret == oldval);
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}
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static inline int64_t opal_atomic_ll_64(volatile int64_t *addr)
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{
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int64_t ret;
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__asm__ __volatile__ ("ldarx %0, 0, %1 \n\t"
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: "=&r" (ret)
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: "r" (addr)
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:);
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return ret;
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}
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static inline int opal_atomic_sc_64(volatile int64_t *addr, int64_t newval)
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{
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int32_t ret, foo;
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__asm__ __volatile__ (" stdcx. %4, 0, %3 \n\t"
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" li %0,0 \n\t"
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" bne- 1f \n\t"
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" ori %0,%0,1 \n\t"
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"1:"
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: "=r" (ret), "=m" (*addr), "=r" (foo)
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: "r" (addr), "r" (newval)
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: "cc", "memory");
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return ret;
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}
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/* these two functions aren't inlined in the non-gcc case because then
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there would be two function calls (since neither cmpset_64 nor
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atomic_?mb can be inlined). Instead, we "inline" them by hand in
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@ -213,6 +286,20 @@ static inline int opal_atomic_cmpset_rel_64(volatile int64_t *addr,
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return opal_atomic_cmpset_64(addr, oldval, newval);
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}
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static inline int64_t opal_atomic_swap_64(volatile int64_t *addr, int64_t newval)
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{
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int64_t ret;
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__asm__ __volatile__ ("1: ldarx %0, 0, %2 \n\t"
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" stdcx. %3, 0, %2 \n\t"
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" bne- 1b \n\t"
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: "=&r" (ret), "=m" (*addr)
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: "r" (addr), "r" (newval)
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: "cc", "memory");
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return ret;
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}
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#endif /* OPAL_GCC_INLINE_ASSEMBLY */
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#elif (OPAL_ASSEMBLY_ARCH == OPAL_POWERPC32) && OPAL_ASM_SUPPORT_64BIT
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