679 строки
23 KiB
C
679 строки
23 KiB
C
/*
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* (c) 2024, SWD Embedded Systems Limited, http://www.kpda.ru
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*/
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/*
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* SUNXI Clock Controller common
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <hw/inout.h>
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#include <clock.h>
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/*
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* Add in the format:
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* X_CLK, shift_bits, mask_parent,
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* {PLL1_*, PLL2_*, PLL3_*, PLL4_*, etc},
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* shift_div_n, shift_div_m
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*
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* PLL1_* = 00
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* PLL2_* = 01
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* PLL3_* = 10
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*
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* etc...
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*/
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static struct clk_parent_map parent_array[] = {
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{
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.entry = THS_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 0,
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.div_n_mask = 0x3,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {OSC_24M},
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},
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{
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.entry = NAND0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = NAND1_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = SDMMC0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
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},
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{
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.entry = SDMMC1_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
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},
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{
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.entry = SDMMC2_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
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},
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{
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.entry = SDMMC3_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
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},
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{
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.entry = TS_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0}
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},
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{
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.entry = SS_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
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},
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{
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.entry = SPI0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = SPI1_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = SPI2_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = SPI3_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = I2S0_CLK,
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.parent_shift_bits = 16,
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.parent_mask_bits = 3 << 16,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
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},
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{
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.entry = I2S1_CLK,
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.parent_shift_bits = 16,
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.parent_mask_bits = 3 << 16,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
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},
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{
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.entry = I2S2_CLK,
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.parent_shift_bits = 16,
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.parent_mask_bits = 3 << 16,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
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},
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{
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.entry = TDM_CLK,
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.parent_shift_bits = 16,
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.parent_mask_bits = 3 << 16,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
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},
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{
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.entry = OWA_CLK,
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.parent_shift_bits = 16,
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.parent_mask_bits = 3 << 16,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
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},
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{
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.entry = KEYPAD_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, UNKNOWN_BIT/*, LOSC*/},
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},
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{
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.entry = SATA_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {PLL_SATA, UNKNOWN_BIT},
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},
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{
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.entry = CIR0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1/*, LOSC*/},
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},
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{
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.entry = CIR1_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1/*, LOSC*/},
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},
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{
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.entry = DRAM_CLK,
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.parent_shift_bits = 20,
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.parent_mask_bits = 3 << 20,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x3,
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.clk_parents = {PLL_DDR0, PLL_DDR1},
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},
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{
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.entry = DE_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_PERIPH0_2X, PLL_DE},
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},
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{
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.entry = DE_MP_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_PERIPH0_2X, PLL_DE},
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},
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{
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.entry = LCD0_TCON_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
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},
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{
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.entry = LCD1_TCON_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
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},
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{
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.entry = TV0_TCON_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
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},
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{
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.entry = TV1_TCON_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
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},
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{
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.entry = DEINTERLACE_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = CSI_MISC_CLK,
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.parent_shift_bits = 8,
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.parent_mask_bits = 7 << 8,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {OSC_24M, PLL_VIDEO1, PLL_PERIPH1},
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},
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{
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.entry = CSI0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 16,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_PERIPH0, PLL_PERIPH1},
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},
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{
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.entry = VE_CLK,
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.parent_shift_bits = 0,
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.parent_mask_bits = 0,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 16,
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.div_m_mask = 0x7,
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.clk_parents = {PLL_VE},
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},
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{
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.entry = ADDA_CLK,
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.parent_shift_bits = 0,
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.parent_mask_bits = 0,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {PLL_AUDIO},
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},
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{
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.entry = AVS_CLK,
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.parent_shift_bits = 0,
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.parent_mask_bits = 0,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {OSC_24M},
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},
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{
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.entry = HDMI0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1},
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},
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{
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.entry = HDMI1_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1}, //???
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},
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{
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.entry = HDMI_SLOW_CLK,
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.parent_shift_bits = 0,
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.parent_mask_bits = 0,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = CLK_NO_DIV_RATIO,
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.div_m_mask = 0x01,
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.clk_parents = {OSC_24M},
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},
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{
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.entry = MBUS0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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.div_n_shift = 16,
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.div_n_mask = 0x3 << 16,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {OSC_24M, PLL_PERIPH0_2X, PLL_DDR0},
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},
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{
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.entry = MIPI_DSI_CLK,
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.parent_shift_bits = 8,
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.parent_mask_bits = 0x3 << 8,
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.div_n_shift = CLK_NO_DIV_RATIO,
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.div_n_mask = 0x01,
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.div_m_shift = 0,
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.div_m_mask = 0x0F,
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.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_PERIPH0},
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},
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{
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.entry = TVE0_CLK,
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.parent_shift_bits = CLK_PARENT_SHIFT,
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.parent_mask_bits = CLK_PARENT_MASK,
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|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x0F,
|
|
.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
|
|
},
|
|
{
|
|
.entry = TVE1_CLK,
|
|
.parent_shift_bits = CLK_PARENT_SHIFT,
|
|
.parent_mask_bits = CLK_PARENT_MASK,
|
|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x0F,
|
|
.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
|
|
},
|
|
{
|
|
.entry = TVD0_CLK,
|
|
.parent_shift_bits = CLK_PARENT_SHIFT,
|
|
.parent_mask_bits = CLK_PARENT_MASK,
|
|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x0F,
|
|
.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
|
|
},
|
|
{
|
|
.entry = TVD1_CLK,
|
|
.parent_shift_bits = CLK_PARENT_SHIFT,
|
|
.parent_mask_bits = CLK_PARENT_MASK,
|
|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x0F,
|
|
.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
|
|
},
|
|
{
|
|
.entry = TVD2_CLK,
|
|
.parent_shift_bits = CLK_PARENT_SHIFT,
|
|
.parent_mask_bits = CLK_PARENT_MASK,
|
|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x0F,
|
|
.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
|
|
},
|
|
{
|
|
.entry = TVD3_CLK,
|
|
.parent_shift_bits = CLK_PARENT_SHIFT,
|
|
.parent_mask_bits = CLK_PARENT_MASK,
|
|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x0F,
|
|
.clk_parents = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
|
|
},
|
|
{
|
|
.entry = GPU_CLK,
|
|
.parent_shift_bits = 0,
|
|
.parent_mask_bits = 0,
|
|
.div_n_shift = CLK_NO_DIV_RATIO,
|
|
.div_n_mask = 0x01,
|
|
.div_m_shift = 0,
|
|
.div_m_mask = 0x3,
|
|
.clk_parents = {PLL_GPU},
|
|
},
|
|
};
|
|
|
|
struct clk_parent_map* get_clk_parent_map(enum sunxi_clk_index clk_id)
|
|
{
|
|
struct clk_parent_map *p = parent_array;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(parent_array); i++, p++)
|
|
{
|
|
if (clk_id == p->entry)
|
|
{
|
|
return p;
|
|
}
|
|
}
|
|
|
|
return (NULL);
|
|
}
|
|
|
|
static struct pll_map pll_array[] = {
|
|
{
|
|
.entry = PLL_CPU0_CTRL,
|
|
.div_p_shift = PLL_FACTOR_P_SHIFT,
|
|
.div_p_mask = 0x03 << PLL_FACTOR_P_SHIFT,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x1F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x03,
|
|
},
|
|
{
|
|
.entry = PLL_AUDIO_CTRL,
|
|
.div_p_shift = PLL_FACTOR_P_SHIFT,
|
|
.div_p_mask = PLL_FACTOR_P_MASK,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = PLL_FACTOR_N_MASK,
|
|
.div_k_shift = CLK_NO_DIV_RATIO,
|
|
.div_k_mask = 0x01,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = PLL_FACTOR_M_MASK,
|
|
},
|
|
{
|
|
.entry = PLL_VIDEO0_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = PLL_FACTOR_N_MASK,
|
|
.div_k_shift = CLK_NO_DIV_RATIO,
|
|
.div_k_mask = 0x01,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x0F,
|
|
},
|
|
{
|
|
.entry = PLL_VIDEO1_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = PLL_FACTOR_N_MASK,
|
|
.div_k_shift = CLK_NO_DIV_RATIO,
|
|
.div_k_mask = 0x01,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x0F,
|
|
},
|
|
{
|
|
.entry = PLL_VE_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = PLL_FACTOR_N_MASK,
|
|
.div_k_shift = CLK_NO_DIV_RATIO,
|
|
.div_k_mask = 0x01,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x0F,
|
|
},
|
|
{
|
|
.entry = PLL_DDR0_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x1F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x03,
|
|
},
|
|
{
|
|
.entry = PLL_DDR1_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x1F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x03,
|
|
},
|
|
{
|
|
.entry = PLL_PERIPH0_CTRL,
|
|
.div_p_shift = PLL_FACTOR_P_SHIFT,
|
|
.div_p_mask = 0x03 << PLL_FACTOR_P_SHIFT,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x1F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x03,
|
|
},
|
|
{
|
|
.entry = PLL_PERIPH1_CTRL,
|
|
.div_p_shift = PLL_FACTOR_P_SHIFT,
|
|
.div_p_mask = 0x03 << PLL_FACTOR_P_SHIFT,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x1F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x03,
|
|
},
|
|
{
|
|
.entry = PLL_GPU_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = PLL_FACTOR_N_MASK,
|
|
.div_k_shift = CLK_NO_DIV_RATIO,
|
|
.div_k_mask = 0x01,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x0F,
|
|
},
|
|
{
|
|
.entry = PLL_DE_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = PLL_FACTOR_N_MASK,
|
|
.div_k_shift = CLK_NO_DIV_RATIO,
|
|
.div_k_mask = 0x01,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x0F,
|
|
},
|
|
{
|
|
.entry = PLL_SATA_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x1F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x03,
|
|
},
|
|
{
|
|
.entry = PLL_MIPI_CTRL,
|
|
.div_p_shift = CLK_NO_DIV_RATIO,
|
|
.div_p_mask = 0x01,
|
|
.div_n_shift = PLL_FACTOR_N_SHIFT,
|
|
.div_n_mask = 0x0F << PLL_FACTOR_N_SHIFT,
|
|
.div_k_shift = PLL_FACTOR_K_SHIFT,
|
|
.div_k_mask = PLL_FACTOR_K_MASK,
|
|
.div_m_shift = PLL_FACTOR_M_SHIFT,
|
|
.div_m_mask = 0x0F,
|
|
},
|
|
};
|
|
|
|
struct pll_map* get_pll_map(enum sunxi_pll_clocks pll_id)
|
|
{
|
|
struct pll_map *p = pll_array;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pll_array); i++, p++)
|
|
{
|
|
if (pll_id == p->entry)
|
|
{
|
|
return p;
|
|
}
|
|
}
|
|
|
|
return (NULL);
|
|
}
|