/*
 * (c) 2024, SWD Embedded Systems Limited, http://www.kpda.ru
 */

/*
 * SUNXI Clock Controller common
 */

#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <errno.h>
#include <hw/inout.h>

#include <clock.h>

/*
 * Add in the format:
 * X_CLK, shift_bits, mask_parent,
 * {PLL1_*, PLL2_*, PLL3_*, PLL4_*, etc},
 * shift_div_n, shift_div_m
 * 
 * PLL1_* = 00
 * PLL2_* = 01
 * PLL3_* = 10
 * 
 * etc...
 */
static struct clk_parent_map parent_array[] = {
    {
        .entry              = THS_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT, 
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 0,
        .div_n_mask         = 0x3,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {OSC_24M},
    },
    {
        .entry              = NAND0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = NAND1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = SDMMC0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
    },
    {
        .entry              = SDMMC1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT, 
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16, 
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0, 
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
    },
    {
        .entry              = SDMMC2_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT, 
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16, 
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0, 
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
    },
    {
        .entry              = SDMMC3_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT, 
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16, 
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
    },
    {
        .entry              = TS_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0}
    },
    {
        .entry              = SS_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0_2X, PLL_PERIPH1_2X},
    },
    {
        .entry              = SPI0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = SPI1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = SPI2_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = SPI3_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = I2S0_CLK,
        .parent_shift_bits  = 16,
        .parent_mask_bits   = 3 << 16,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
    },
    {
        .entry              = I2S1_CLK,
        .parent_shift_bits  = 16,
        .parent_mask_bits   = 3 << 16,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
    },
    {
        .entry              = I2S2_CLK,
        .parent_shift_bits  = 16,
        .parent_mask_bits   = 3 << 16,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
    },
    {
        .entry              = TDM_CLK,
        .parent_shift_bits  = 16,
        .parent_mask_bits   = 3 << 16,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
    },
    {
        .entry              = OWA_CLK,
        .parent_shift_bits  = 16,
        .parent_mask_bits   = 3 << 16,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_AUDIO_8X, PLL_AUDIO_4X, PLL_AUDIO_2X, PLL_AUDIO},
    },
    {
        .entry              = KEYPAD_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, UNKNOWN_BIT/*, LOSC*/},
    },
    {
        .entry              = SATA_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {PLL_SATA, UNKNOWN_BIT},
    },
    {
        .entry              = CIR0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1/*, LOSC*/},
    },
    {
        .entry              = CIR1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0, PLL_PERIPH1/*, LOSC*/},
    },
    {
        .entry              = DRAM_CLK,
        .parent_shift_bits  = 20,
        .parent_mask_bits   = 3 << 20,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x3,
        .clk_parents        = {PLL_DDR0, PLL_DDR1},
    },
    {
        .entry              = DE_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_PERIPH0_2X, PLL_DE},
    },
    {
        .entry              = DE_MP_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_PERIPH0_2X, PLL_DE},
    },
    {
        .entry              = LCD0_TCON_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
    },
    {
        .entry              = LCD1_TCON_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
    },
    {
        .entry              = TV0_TCON_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
    },
    {
        .entry              = TV1_TCON_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
    },
    {
        .entry              = DEINTERLACE_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = CSI_MISC_CLK,
        .parent_shift_bits  = 8,
        .parent_mask_bits   = 7 << 8,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {OSC_24M, PLL_VIDEO1, PLL_PERIPH1},
    },
    {
        .entry              = CSI0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 16,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_PERIPH0, PLL_PERIPH1},
    },
    {
        .entry              = VE_CLK,
        .parent_shift_bits  = 0,
        .parent_mask_bits   = 0,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 16,
        .div_m_mask         = 0x7,
        .clk_parents        = {PLL_VE},
    },
    {
        .entry              = ADDA_CLK,
        .parent_shift_bits  = 0,
        .parent_mask_bits   = 0,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {PLL_AUDIO},
    },
    {
        .entry              = AVS_CLK,
        .parent_shift_bits  = 0,
        .parent_mask_bits   = 0,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {OSC_24M},
    },
    {
        .entry              = HDMI0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1},
    },
    {
        .entry              = HDMI1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1}, //???
    },
    {
        .entry              = HDMI_SLOW_CLK,
        .parent_shift_bits  = 0,
        .parent_mask_bits   = 0,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = CLK_NO_DIV_RATIO,
        .div_m_mask         = 0x01,
        .clk_parents        = {OSC_24M},
    },
    {
        .entry              = MBUS0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = 16,
        .div_n_mask         = 0x3 << 16,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {OSC_24M, PLL_PERIPH0_2X, PLL_DDR0},
    },
    {
        .entry              = MIPI_DSI_CLK,
        .parent_shift_bits  = 8,
        .parent_mask_bits   = 0x3 << 8,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_PERIPH0},
    },
    {
        .entry              = TVE0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
    },
    {
        .entry              = TVE1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X, PLL_MIPI},
    },
    {
        .entry              = TVD0_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
    },
    {
        .entry              = TVD1_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
    },
    {
        .entry              = TVD2_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
    },
    {
        .entry              = TVD3_CLK,
        .parent_shift_bits  = CLK_PARENT_SHIFT,
        .parent_mask_bits   = CLK_PARENT_MASK,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x0F,
        .clk_parents        = {PLL_VIDEO0, PLL_VIDEO1, PLL_VIDEO0_2X, PLL_VIDEO1_2X},
    },
    {
        .entry              = GPU_CLK,
        .parent_shift_bits  = 0,
        .parent_mask_bits   = 0,
        .div_n_shift        = CLK_NO_DIV_RATIO,
        .div_n_mask         = 0x01,
        .div_m_shift        = 0,
        .div_m_mask         = 0x3,
        .clk_parents        = {PLL_GPU},
    },
};

struct clk_parent_map* get_clk_parent_map(enum sunxi_clk_index clk_id)
{
    struct clk_parent_map   *p = parent_array;
    int                     i;

    for (i = 0; i < ARRAY_SIZE(parent_array); i++, p++)
    {
        if (clk_id == p->entry)
        {
            return p;
        }
    }

    return (NULL);
}

static struct pll_map pll_array[] = {
    {
        .entry          = PLL_CPU0_CTRL,
        .div_p_shift    = PLL_FACTOR_P_SHIFT,
        .div_p_mask     = 0x03 << PLL_FACTOR_P_SHIFT,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x1F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x03,
    },
    {
        .entry          = PLL_AUDIO_CTRL,
        .div_p_shift    = PLL_FACTOR_P_SHIFT,
        .div_p_mask     = PLL_FACTOR_P_MASK,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = PLL_FACTOR_N_MASK,
        .div_k_shift    = CLK_NO_DIV_RATIO,
        .div_k_mask     = 0x01, 
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = PLL_FACTOR_M_MASK,
    },
    {
        .entry          = PLL_VIDEO0_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = PLL_FACTOR_N_MASK,
        .div_k_shift    = CLK_NO_DIV_RATIO,
        .div_k_mask     = 0x01, 
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x0F,
    },
    {
        .entry          = PLL_VIDEO1_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = PLL_FACTOR_N_MASK,
        .div_k_shift    = CLK_NO_DIV_RATIO,
        .div_k_mask     = 0x01,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x0F,
    },
    {
        .entry          = PLL_VE_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = PLL_FACTOR_N_MASK,
        .div_k_shift    = CLK_NO_DIV_RATIO,
        .div_k_mask     = 0x01,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x0F,
    },
    {
        .entry          = PLL_DDR0_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x1F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x03,
    },
    {
        .entry          = PLL_DDR1_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x1F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x03,
    },
    {
        .entry          = PLL_PERIPH0_CTRL,
        .div_p_shift    = PLL_FACTOR_P_SHIFT,
        .div_p_mask     = 0x03 << PLL_FACTOR_P_SHIFT,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x1F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x03,
    },
    {
        .entry          = PLL_PERIPH1_CTRL,
        .div_p_shift    = PLL_FACTOR_P_SHIFT,
        .div_p_mask     = 0x03 << PLL_FACTOR_P_SHIFT,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x1F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x03,
    },
    {
        .entry          = PLL_GPU_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = PLL_FACTOR_N_MASK,
        .div_k_shift    = CLK_NO_DIV_RATIO,
        .div_k_mask     = 0x01,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x0F,
    },
    {
        .entry          = PLL_DE_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = PLL_FACTOR_N_MASK,
        .div_k_shift    = CLK_NO_DIV_RATIO,
        .div_k_mask     = 0x01,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x0F,
    },
    {
        .entry          = PLL_SATA_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x1F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x03,
    },
    {
        .entry          = PLL_MIPI_CTRL,
        .div_p_shift    = CLK_NO_DIV_RATIO,
        .div_p_mask     = 0x01,
        .div_n_shift    = PLL_FACTOR_N_SHIFT,
        .div_n_mask     = 0x0F << PLL_FACTOR_N_SHIFT,
        .div_k_shift    = PLL_FACTOR_K_SHIFT,
        .div_k_mask     = PLL_FACTOR_K_MASK,
        .div_m_shift    = PLL_FACTOR_M_SHIFT,
        .div_m_mask     = 0x0F,
    },
};

struct pll_map* get_pll_map(enum sunxi_pll_clocks pll_id)
{
    struct pll_map   *p = pll_array;
    int              i;

    for (i = 0; i < ARRAY_SIZE(pll_array); i++, p++)
    {
        if (pll_id == p->entry)
        {
            return p;
        }
    }

    return (NULL);
}