b3cc58b681
moving the tick register to another register, but is fine with rd. * properly mask out the upper 32 bits of the register containing the lower 32 bits so that the or with the upper 32bits actually works properly. Hopefully, gcc will optimize this into code that doesn't suck so much (it's much easier to deal with when you get to control the argument registers...) This commit was SVN r7410.
66 строки
1.4 KiB
C
66 строки
1.4 KiB
C
/*
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* Copyright (c) 2004-2005 The Trustees of Indiana University.
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* All rights reserved.
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* Copyright (c) 2004-2005 The Trustees of the University of Tennessee.
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* All rights reserved.
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* Copyright (c) 2004-2005 High Performance Computing Center Stuttgart,
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* University of Stuttgart. All rights reserved.
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* Copyright (c) 2004-2005 The Regents of the University of California.
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* All rights reserved.
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* $COPYRIGHT$
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*
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* Additional copyrights may follow
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*
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* $HEADER$
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*/
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#ifndef OMPI_SYS_ARCH_TIMER_H
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#define OMPI_SYS_ARCH_TIMER_H 1
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typedef uint64_t opal_timer_t;
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#if OMPI_GCC_INLINE_ASSEMBLY
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#if OMPI_ASSEMBLY_ARCH == OMPI_SPARCV9_64
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static inline opal_timer_t
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opal_sys_timer_get_cycles(void)
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{
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opal_timer_t ret;
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__asm__ __volatile__("rd %%tick, %0" : "=r"(ret));
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return ret;
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}
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#else /* OMPI_SPARCV9_32 */
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static inline opal_timer_t
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opal_sys_timer_get_cycles(void)
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{
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opal_timer_t ret;
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int a, b;
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__asm__ __volatile__("rd %%tick, %0 \n"
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"srlx %0, 32, %1 " :
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"=r"(a), "=r"(b)
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);
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ret = (0x00000000FFFFFFFF & a) | (((opal_timer_t) b) << 32);
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return ret;
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}
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#endif
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#define OPAL_HAVE_SYS_TIMER_GET_CYCLES 1
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#else
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#define OPAL_HAVE_SYS_TIMER_GET_CYCLES 0
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#endif /* OMPI_GCC_INLINE_ASSEMBLY */
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#endif /* ! OMPI_SYS_ARCH_TIMER_H */
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