194 строки
5.0 KiB
C
194 строки
5.0 KiB
C
/*
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* Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
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* University Research and Technology
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* Corporation. All rights reserved.
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* Copyright (c) 2004-2005 The University of Tennessee and The University
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* of Tennessee Research Foundation. All rights
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* reserved.
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* Copyright (c) 2004-2005 High Performance Computing Center Stuttgart,
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* University of Stuttgart. All rights reserved.
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* Copyright (c) 2004-2005 The Regents of the University of California.
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* All rights reserved.
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* $COPYRIGHT$
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*
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* Additional copyrights may follow
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*
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* $HEADER$
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*/
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#ifndef OMPI_SYS_ARCH_ATOMIC_H
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#define OMPI_SYS_ARCH_ATOMIC_H 1
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/*
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* On sparc v9, use casa and casxa (compare and swap) instructions.
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*/
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#define ASI_P "0x80"
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#if OMPI_WANT_SMP_LOCKS
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#define MEMBAR(type) __asm__ __volatile__ ("membar " type : : : "memory")
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#else
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#define MEMBAR(type)
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#endif
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/**********************************************************************
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*
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* Define constants for Sparc v9 (Ultra Sparc)
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*
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*********************************************************************/
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#define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
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#define OPAL_HAVE_ATOMIC_CMPSET_32 1
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#define OPAL_HAVE_ATOMIC_CMPSET_64 1
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/**********************************************************************
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*
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* Memory Barriers
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*
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*********************************************************************/
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#if OMPI_GCC_INLINE_ASSEMBLY
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static inline void opal_atomic_mb(void)
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{
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MEMBAR("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad");
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}
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static inline void opal_atomic_rmb(void)
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{
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MEMBAR("#LoadLoad");
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}
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static inline void opal_atomic_wmb(void)
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{
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MEMBAR("#StoreStore");
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}
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#endif /* OMPI_GCC_INLINE_ASSEMBLY */
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/**********************************************************************
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*
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* Atomic math operations
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*
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*********************************************************************/
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#if OMPI_GCC_INLINE_ASSEMBLY
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static inline int opal_atomic_cmpset_32( volatile int32_t *addr,
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int32_t oldval, int32_t newval)
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{
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/* casa [reg(rs1)] %asi, reg(rs2), reg(rd)
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*
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* if (*(reg(rs1)) == reg(rs1) )
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* swap reg(rd), *(reg(rs1))
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* else
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* reg(rd) = *(reg(rs1))
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*/
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int32_t ret = newval;
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__asm__ __volatile("casa [%1] " ASI_P ", %2, %0"
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: "+r" (ret)
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: "r" (addr), "r" (oldval));
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return (ret == oldval);
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}
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static inline int opal_atomic_cmpset_acq_32( volatile int32_t *addr,
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int32_t oldval, int32_t newval)
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{
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int rc;
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rc = opal_atomic_cmpset_32(addr, oldval, newval);
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opal_atomic_rmb();
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return rc;
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}
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static inline int opal_atomic_cmpset_rel_32( volatile int32_t *addr,
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int32_t oldval, int32_t newval)
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{
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opal_atomic_wmb();
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return opal_atomic_cmpset_32(addr, oldval, newval);
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}
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#if OMPI_ASSEMBLY_ARCH == OMPI_SPARCV9_64
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static inline int opal_atomic_cmpset_64( volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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/* casa [reg(rs1)] %asi, reg(rs2), reg(rd)
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*
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* if (*(reg(rs1)) == reg(rs1) )
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* swap reg(rd), *(reg(rs1))
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* else
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* reg(rd) = *(reg(rs1))
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*/
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int64_t ret = newval;
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__asm__ __volatile("casxa [%1] " ASI_P ", %2, %0"
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: "+r" (ret)
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: "r" (addr), "r" (oldval));
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return (ret == oldval);
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}
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#else /* OMPI_ASSEMBLY_ARCH == OMPI_SPARCV9_64 */
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static inline int opal_atomic_cmpset_64( volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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/* casa [reg(rs1)] %asi, reg(rs2), reg(rd)
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*
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* if (*(reg(rs1)) == reg(rs1) )
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* swap reg(rd), *(reg(rs1))
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* else
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* reg(rd) = *(reg(rs1))
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*
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*/
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long long ret = newval;
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__asm__ __volatile(
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"ldx %0, %%g1 \n\t" /* g1 = ret */
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"ldx %2, %%g2 \n\t" /* g2 = oldval */
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"casxa [%1] " ASI_P ", %%g2, %%g1 \n\t"
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"stx %%g1, %0 \n"
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: "=m"(ret)
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: "r"(addr), "m"(oldval)
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: "%g1", "%g2"
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);
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return (ret == oldval);
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}
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#endif /* OMPI_ASSEMBLY_ARCH == OMPI_SPARCV9_64 */
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static inline int opal_atomic_cmpset_acq_64( volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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int rc;
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rc = opal_atomic_cmpset_64(addr, oldval, newval);
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opal_atomic_rmb();
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return rc;
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}
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static inline int opal_atomic_cmpset_rel_64( volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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opal_atomic_wmb();
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return opal_atomic_cmpset_64(addr, oldval, newval);
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}
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#endif /* OMPI_GCC_INLINE_ASSEMBLY */
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#endif /* ! OMPI_SYS_ARCH_ATOMIC_H */
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