147 строки
3.8 KiB
C
147 строки
3.8 KiB
C
/*
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* Copyright (c) 2004-2005 The Trustees of Indiana University and Indiana
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* University Research and Technology
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* Corporation. All rights reserved.
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* Copyright (c) 2004-2005 The University of Tennessee and The University
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* of Tennessee Research Foundation. All rights
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* reserved.
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* Copyright (c) 2004-2005 High Performance Computing Center Stuttgart,
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* University of Stuttgart. All rights reserved.
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* Copyright (c) 2004-2005 The Regents of the University of California.
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* All rights reserved.
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* $COPYRIGHT$
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*
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* Additional copyrights may follow
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*
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* $HEADER$
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*/
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#ifndef OMPI_SYS_ARCH_ATOMIC_H
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#define OMPI_SYS_ARCH_ATOMIC_H 1
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/*
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* On ia64, we use cmpxchg, which supports acquire/release semantics natively.
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*/
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#if OMPI_WANT_SMP_LOCKS
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#define MB() __asm__ __volatile__("": : :"memory")
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#else
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#define MB()
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#endif
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/**********************************************************************
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*
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* Define constants for IA64
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*
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*********************************************************************/
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#define OPAL_HAVE_ATOMIC_MEM_BARRIER 1
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#define OPAL_HAVE_ATOMIC_CMPSET_32 1
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#define OPAL_HAVE_ATOMIC_CMPSET_64 1
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/**********************************************************************
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*
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* Memory Barriers
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*
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*********************************************************************/
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#if OMPI_GCC_INLINE_ASSEMBLY
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static inline void opal_atomic_mb(void)
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{
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MB();
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}
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static inline void opal_atomic_rmb(void)
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{
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MB();
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}
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static inline void opal_atomic_wmb(void)
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{
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MB();
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}
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#endif /* OMPI_GCC_INLINE_ASSEMBLY */
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/**********************************************************************
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*
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* Atomic math operations
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*
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*********************************************************************/
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#if OMPI_GCC_INLINE_ASSEMBLY
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#define ia64_cmpxchg4_acq(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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ia64_intri_res; \
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})
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static inline int opal_atomic_cmpset_acq_32( volatile int32_t *addr,
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int32_t oldval, int32_t newval)
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{
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int64_t ret;
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__asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(oldval));
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__asm__ __volatile__ ("cmpxchg4.acq %0=[%1],%2,ar.ccv":
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"=r"(ret) : "r"(addr), "r"(newval) : "memory");
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return ((int32_t)ret == oldval);
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}
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static inline int opal_atomic_cmpset_rel_32( volatile int32_t *addr,
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int32_t oldval, int32_t newval)
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{
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int64_t ret;
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__asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(oldval));
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__asm__ __volatile__ ("cmpxchg4.rel %0=[%1],%2,ar.ccv":
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"=r"(ret) : "r"(addr), "r"(newval) : "memory");
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return ((int32_t)ret == oldval);
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}
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#endif /* OMPI_GCC_INLINE_ASSEMBLY */
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#define opal_atomic_cmpset_32 opal_atomic_cmpset_acq_32
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#if OMPI_GCC_INLINE_ASSEMBLY
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static inline int opal_atomic_cmpset_acq_64( volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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int64_t ret;
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__asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(oldval));
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__asm__ __volatile__ ("cmpxchg8.acq %0=[%1],%2,ar.ccv":
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"=r"(ret) : "r"(addr), "r"(newval) : "memory");
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return ((int32_t)ret == oldval);
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}
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static inline int opal_atomic_cmpset_rel_64( volatile int64_t *addr,
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int64_t oldval, int64_t newval)
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{
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int64_t ret;
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__asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(oldval));
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__asm__ __volatile__ ("cmpxchg8.rel %0=[%1],%2,ar.ccv":
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"=r"(ret) : "r"(addr), "r"(newval) : "memory");
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return ((int32_t)ret == oldval);
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}
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#endif /* OMPI_GCC_INLINE_ASSEMBLY */
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#define opal_atomic_cmpset_64 opal_atomic_cmpset_acq_64
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#endif /* ! OMPI_SYS_ARCH_ATOMIC_H */
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