Per discussion on the devel list, revert r27882.
Leif would like to revamp the ARM support in a different way, and will submit a patch to do so in the future. This commit was SVN r27960. The following SVN revision numbers were found above: r27882 --> open-mpi/ompi@8649b5eece
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родитель
7993d57c24
Коммит
ef8ab5507e
@ -811,7 +811,6 @@ AC_DEFUN([OPAL_CONFIG_ASM],[
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ompi_cv_asm_arch="ARM"
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OPAL_ASM_SUPPORT_64BIT=1
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OPAL_ASM_ARM_VERSION=7
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cp -f "$top_ompi_builddir/opal/asm/base/ARMV7.asm" "$top_ompi_builddir/opal/asm/base/ARM.asm"
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AC_DEFINE_UNQUOTED([OPAL_ASM_ARM_VERSION], [$OPAL_ASM_ARM_VERSION],
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[What ARM assembly version to use])
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OMPI_GCC_INLINE_ASSIGN='"mov %0, #0" : "=&r"(ret)'
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@ -821,7 +820,6 @@ AC_DEFUN([OPAL_CONFIG_ASM],[
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ompi_cv_asm_arch="ARM"
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OPAL_ASM_SUPPORT_64BIT=0
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OPAL_ASM_ARM_VERSION=6
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cp -f "$top_ompi_builddir/opal/asm/base/ARMV6.asm" "$top_ompi_builddir/opal/asm/base/ARM.asm"
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AC_DEFINE_UNQUOTED([OPAL_ASM_ARM_VERSION], [$OPAL_ASM_ARM_VERSION],
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[What ARM assembly version to use])
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OMPI_GCC_INLINE_ASSIGN='"mov %0, #0" : "=&r"(ret)'
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@ -832,7 +830,6 @@ AC_DEFUN([OPAL_CONFIG_ASM],[
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ompi_cv_asm_arch="ARM"
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OPAL_ASM_SUPPORT_64BIT=0
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OPAL_ASM_ARM_VERSION=5
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cp -f "$top_ompi_builddir/opal/asm/base/ARMV5.asm" "$top_ompi_builddir/opal/asm/base/ARM.asm"
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AC_DEFINE_UNQUOTED([OPAL_ASM_ARM_VERSION], [$OPAL_ASM_ARM_VERSION],
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[What ARM assembly version to use])
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OMPI_GCC_INLINE_ASSIGN='"mov %0, #0" : "=&r"(ret)'
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@ -65,9 +65,7 @@ EXTRA_DIST = \
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base/default.conf \
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base/ALPHA.asm \
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base/AMD64.asm \
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base/ARMV5.asm \
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base/ARMV6.asm \
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base/ARMV7.asm \
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base/ARM.asm \
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base/IA32.asm \
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base/IA64.asm \
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base/MIPS.asm \
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@ -1,109 +0,0 @@
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START_FILE
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TEXT
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ALIGN(4)
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START_FUNC(opal_atomic_mb)
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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END_FUNC(opal_atomic_mb)
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START_FUNC(opal_atomic_rmb)
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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END_FUNC(opal_atomic_rmb)
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START_FUNC(opal_atomic_wmb)
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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END_FUNC(opal_atomic_wmb)
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START_FUNC(opal_atomic_cmpset_32)
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push {r4, lr}
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mov r3, r0
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mov r0, r1
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mov r1, r2
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mov r2, r3
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ldr r3, REFLSYM(1)
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blx r3
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movcc r0, #0
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movcs r0, #1
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pop {r4, lr}
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bx lr
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.align 2
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LSYM(1)
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.word 0xffff0fc0
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END_FUNC(opal_atomic_cmpset_32)
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START_FUNC(opal_atomic_cmpset_acq_32)
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push {r4, lr}
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mov r3, r0
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mov r0, r1
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mov r1, r2
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mov r2, r3
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ldr r3, REFLSYM(2)
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blx r3
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movcc r0, #0
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movcs r0, #1
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pop {r4, lr}
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bx lr
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.align 2
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LSYM(2)
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.word 0xffff0fc0
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END_FUNC(opal_atomic_cmpset_acq_32)
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START_FUNC(opal_atomic_cmpset_rel_32)
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push {r4, lr}
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mov r3, r0
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mov r0, r1
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mov r1, r2
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mov r2, r3
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ldr r3, REFLSYM(3)
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blx r3
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movcc r0, #0
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movcs r0, #1
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pop {r4, lr}
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bx lr
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.align 2
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LSYM(3)
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.word 0xffff0fc0
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END_FUNC(opal_atomic_cmpset_rel_32)
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START_FUNC(opal_atomic_add_32)
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push {r4, lr}
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mov r4, r1
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mov r2, r0
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LSYM(4)
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ldr r0, [r2]
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ldr r3, REFLSYM(5)
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add r1, r0, r4
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blx r3
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bcc REFLSYM(4)
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pop {r4, lr}
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bx lr
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.align 2
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LSYM(5)
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.word 0xffff0fc0
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END_FUNC(opal_atomic_add_32)
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START_FUNC(opal_atomic_sub_32)
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push {r4, lr}
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mov r4, r1
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mov r2, r0
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LSYM(6)
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ldr r0, [r2]
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ldr r3, REFLSYM(7)
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sub r1, r0, r4
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blx r3
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bcc REFLSYM(6)
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pop {r4, lr}
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bx lr
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.align 2
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LSYM(7)
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.word 0xffff0fc0
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END_FUNC(opal_atomic_sub_32)
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@ -1,153 +0,0 @@
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START_FILE
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TEXT
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ALIGN(4)
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START_FUNC(opal_atomic_mb)
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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END_FUNC(opal_atomic_mb)
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START_FUNC(opal_atomic_rmb)
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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END_FUNC(opal_atomic_rmb)
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START_FUNC(opal_atomic_wmb)
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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END_FUNC(opal_atomic_wmb)
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START_FUNC(opal_atomic_cmpset_32)
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LSYM(1)
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ldrex r3, [r0]
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cmp r1, r3
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bne REFLSYM(2)
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strex r12, r2, [r0]
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cmp r12, #0
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bne REFLSYM(1)
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mov r0, #1
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LSYM(2)
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movne r0, #0
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bx lr
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END_FUNC(opal_atomic_cmpset_32)
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START_FUNC(opal_atomic_cmpset_acq_32)
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LSYM(3)
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ldrex r3, [r0]
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cmp r1, r3
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bne REFLSYM(4)
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strex r12, r2, [r0]
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cmp r12, #0
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bne REFLSYM(3)
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dmb
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mov r0, #1
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LSYM(4)
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movne r0, #0
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bx lr
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END_FUNC(opal_atomic_cmpset_acq_32)
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START_FUNC(opal_atomic_cmpset_rel_32)
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LSYM(5)
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ldrex r3, [r0]
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cmp r1, r3
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bne REFLSYM(6)
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dmb
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strex r12, r2, [r0]
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cmp r12, #0
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bne REFLSYM(4)
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mov r0, #1
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LSYM(6)
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movne r0, #0
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bx lr
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END_FUNC(opal_atomic_cmpset_rel_32)
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#START_64BIT
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START_FUNC(opal_atomic_cmpset_64)
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push {r4-r7}
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ldrd r6, r7, [sp, #16]
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LSYM(7)
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ldrexd r4, r5, [r0]
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cmp r4, r2
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it eq
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cmpeq r5, r3
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bne REFLSYM(8)
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strexd r1, r6, r7, [r0]
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cmp r1, #0
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bne REFLSYM(7)
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mov r0, #1
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LSYM(8)
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movne r0, #0
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pop {r4-r7}
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bx lr
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END_FUNC(opal_atomic_cmpset_64)
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START_FUNC(opal_atomic_cmpset_acq_64)
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push {r4-r7}
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ldrd r6, r7, [sp, #16]
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LSYM(9)
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ldrexd r4, r5, [r0]
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cmp r4, r2
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it eq
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cmpeq r5, r3
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bne REFLSYM(10)
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strexd r1, r6, r7, [r0]
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cmp r1, #0
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bne REFLSYM(9)
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dmb
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mov r0, #1
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LSYM(10)
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movne r0, #0
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pop {r4-r7}
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bx lr
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END_FUNC(opal_atomic_cmpset_acq_64)
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START_FUNC(opal_atomic_cmpset_rel_64)
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push {r4-r7}
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ldrd r6, r7, [sp, #16]
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LSYM(11)
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ldrexd r4, r5, [r0]
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cmp r4, r2
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it eq
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cmpeq r5, r3
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bne REFLSYM(12)
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dmb
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strexd r1, r6, r7, [r0]
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cmp r1, #0
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bne REFLSYM(11)
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mov r0, #1
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LSYM(12)
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movne r0, #0
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pop {r4-r7}
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bx lr
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END_FUNC(opal_atomic_cmpset_rel_64)
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#END_64BIT
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START_FUNC(opal_atomic_add_32)
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LSYM(13)
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ldrex r2, [r0]
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add r2, r2, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne REFLSYM(13)
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mov r0, r2
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bx lr
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END_FUNC(opal_atomic_add_32)
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START_FUNC(opal_atomic_sub_32)
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LSYM(14)
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ldrex r2, [r0]
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sub r2, r2, r1
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strex r3, r2, [r0]
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cmp r3, #0
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bne REFLSYM(14)
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mov r0, r2
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bx lr
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END_FUNC(opal_atomic_sub_32)
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