* Update to include IA64, which passes all tests in the test suite

This commit was SVN r4471.

src/asm/asm-data.txt

@@ -48,6 +48,8 @@ IA32	default-.text-.globl-:--.L-@-1-0-1-1	ia32-linux
 #
 ######################################################################
 
+IA64	default-.text-.globl-:--.L-@-1-0-1-1	ia64-linux
+
 
 ######################################################################
 #
@@ -102,4 +104,4 @@ SPARCV9_64	default-.text-.globl-:--.L-#-1-0-1-1	sparcv9-64-solaris
 # in one register (instead of SPARC and POWER, who use two).  Which
 # means that we can use the same code either way.  Woo hoo!
 
-MIPS3	default-.text-.globl-:--L--1-1-1-1	mips-irix
+MIPS	default-.text-.globl-:--L--1-1-1-1	mips-irix

src/asm/asm.c

@@ -17,7 +17,7 @@
 #include "include/sys/atomic.h"
 #include "include/sys/architecture.h"
 
-#if OMPI_ASSEMBLY_ARCH == OMPI_SPARC32
+#if OMPI_ASSEMBLY_ARCH == OMPI_SPARC
 
 #if OMPI_WANT_SMP_LOCKS
 

src/asm/base/IA64.asm

@@ -0,0 +1,108 @@
+START_FILE
+
+	.pred.safe_across_calls p1-p5,p16-p63
+	.text
+	.align 16
+	.global ompi_atomic_mb#
+	.proc ompi_atomic_mb#
+ompi_atomic_mb:
+	.prologue
+	.body
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_mb#
+	.align 16
+	.global ompi_atomic_rmb#
+	.proc ompi_atomic_rmb#
+ompi_atomic_rmb:
+	.prologue
+	.body
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_rmb#
+	.align 16
+	.global ompi_atomic_wmb#
+	.proc ompi_atomic_wmb#
+ompi_atomic_wmb:
+	.prologue
+	.body
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_wmb#
+	.align 16
+	.global ompi_atomic_cmpset_acq_32#
+	.proc ompi_atomic_cmpset_acq_32#
+ompi_atomic_cmpset_acq_32:
+	.prologue
+	.body
+#APP
+	mov ar.ccv=r33;;
+	cmpxchg4.acq r32=[r32],r34,ar.ccv
+#NO_APP
+	;;
+	cmp4.eq p6, p7 = r32, r33
+	;;
+	(p6) addl r8 = 1, r0
+	(p7) mov r8 = r0
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_cmpset_acq_32#
+	.align 16
+	.global ompi_atomic_cmpset_rel_32#
+	.proc ompi_atomic_cmpset_rel_32#
+ompi_atomic_cmpset_rel_32:
+	.prologue
+	.body
+#APP
+	mov ar.ccv=r33;;
+	cmpxchg4.rel r32=[r32],r34,ar.ccv
+#NO_APP
+	;;
+	cmp4.eq p6, p7 = r32, r33
+	;;
+	(p6) addl r8 = 1, r0
+	(p7) mov r8 = r0
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_cmpset_rel_32#
+	.align 16
+	.global ompi_atomic_cmpset_acq_64#
+	.proc ompi_atomic_cmpset_acq_64#
+ompi_atomic_cmpset_acq_64:
+	.prologue
+	.body
+#APP
+	mov ar.ccv=r33;;
+	cmpxchg8.acq r32=[r32],r34,ar.ccv
+#NO_APP
+	;;
+	sxt4 r32 = r32
+	;;
+	cmp.eq p6, p7 = r33, r32
+	;;
+	(p6) addl r8 = 1, r0
+	(p7) mov r8 = r0
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_cmpset_acq_64#
+	.align 16
+	.global ompi_atomic_cmpset_rel_64#
+	.proc ompi_atomic_cmpset_rel_64#
+ompi_atomic_cmpset_rel_64:
+	.prologue
+	.body
+#APP
+	mov ar.ccv=r33;;
+	cmpxchg8.rel r32=[r32],r34,ar.ccv
+#NO_APP
+	;;
+	sxt4 r32 = r32
+	;;
+	cmp.eq p6, p7 = r33, r32
+	;;
+	(p6) addl r8 = 1, r0
+	(p7) mov r8 = r0
+	br.ret.sptk.many b0
+	;;
+	.endp ompi_atomic_cmpset_rel_64#
+	.ident	"GCC: (GNU) 3.2.3 20030502 (Red Hat Linux 3.2.3-49)"

src/include/sys/ia64/atomic.h

@@ -32,10 +32,10 @@
  * Define constants for IA64
  *
  *********************************************************************/
-#define OMPI_HAVE_MEM_BARRIER 1
+#define OMPI_HAVE_ATOMIC_MEM_BARRIER 1
 
-#define OMPI_HAVE_ATOMIC_CMPSET_32
-#define OMPI_HAVE_ATOMIC_CMPSET_64
+#define OMPI_HAVE_ATOMIC_CMPSET_32 1
+#define OMPI_HAVE_ATOMIC_CMPSET_64 1
 
 /**********************************************************************
  *

src/include/sys/ia64/update.sh

@@ -29,4 +29,4 @@ cat > $CFILE<<EOF
 #include "atomic.h"
 EOF
 
-gcc -I. -S $CFILE -o atomic.s
+gcc -O1 -I. -S $CFILE -o atomic.s