asm/arm64: ensure instruction ordering on timer
Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
Этот коммит содержится в:
родитель
432d79046b
Коммит
9a50ce6364
@ -1,8 +1,11 @@
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/* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil -*- */
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/*
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/*
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* Copyright (c) 2008 The University of Tennessee and The University
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* Copyright (c) 2008 The University of Tennessee and The University
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* of Tennessee Research Foundation. All rights
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* of Tennessee Research Foundation. All rights
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* reserved.
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* reserved.
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* Copyright (c) 2016 Broadcom Limited. All rights reserved.
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* Copyright (c) 2016 Broadcom Limited. All rights reserved.
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* Copyright (c) 2016 Los Alamos National Security, LLC. All rights
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* reserved.
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* $COPYRIGHT$
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* $COPYRIGHT$
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*
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*
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* Additional copyrights may follow
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* Additional copyrights may follow
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@ -22,6 +25,7 @@ opal_sys_timer_get_cycles(void)
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{
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{
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opal_timer_t ret;
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opal_timer_t ret;
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__asm__ __volatile__ ("isb" ::: "memory");
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__asm__ __volatile__ ("mrs %0, CNTVCT_EL0" : "=r" (ret));
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__asm__ __volatile__ ("mrs %0, CNTVCT_EL0" : "=r" (ret));
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return ret;
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return ret;
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