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asm/arm64: ensure instruction ordering on timer

Signed-off-by: Nathan Hjelm <hjelmn@lanl.gov>
Этот коммит содержится в:
Nathan Hjelm 2016-10-11 12:14:03 -06:00
родитель 432d79046b
Коммит 9a50ce6364

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@ -1,8 +1,11 @@
/* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil -*- */
/* /*
* Copyright (c) 2008 The University of Tennessee and The University * Copyright (c) 2008 The University of Tennessee and The University
* of Tennessee Research Foundation. All rights * of Tennessee Research Foundation. All rights
* reserved. * reserved.
* Copyright (c) 2016 Broadcom Limited. All rights reserved. * Copyright (c) 2016 Broadcom Limited. All rights reserved.
* Copyright (c) 2016 Los Alamos National Security, LLC. All rights
* reserved.
* $COPYRIGHT$ * $COPYRIGHT$
* *
* Additional copyrights may follow * Additional copyrights may follow
@ -22,6 +25,7 @@ opal_sys_timer_get_cycles(void)
{ {
opal_timer_t ret; opal_timer_t ret;
__asm__ __volatile__ ("isb" ::: "memory");
__asm__ __volatile__ ("mrs %0, CNTVCT_EL0" : "=r" (ret)); __asm__ __volatile__ ("mrs %0, CNTVCT_EL0" : "=r" (ret));
return ret; return ret;