Fix ia64 operations by correcting a couple of bugs in the ia64 atomics. Thanks to Paul Hargrove for the patch!

Since Paul is the only one of the team with the required hardware to test it, and he has done so, consider this RM-approved.

cmr=v1.7.5:reviewer=ompi-gk1.7

This commit was SVN r30401.

opal/asm/base/IA64.asm

@@ -73,8 +73,6 @@ opal_atomic_cmpset_acq_64:
 	mov ar.ccv=r33;;
 	cmpxchg8.acq r32=[r32],r34,ar.ccv
 	;;
-	sxt4 r32 = r32
-	;;
 	cmp.eq p6, p7 = r33, r32
 	;;
 	(p6) addl r8 = 1, r0
@@ -91,8 +89,6 @@ opal_atomic_cmpset_rel_64:
 	mov ar.ccv=r33;;
 	cmpxchg8.rel r32=[r32],r34,ar.ccv
 	;;
-	sxt4 r32 = r32
-	;;
 	cmp.eq p6, p7 = r33, r32
 	;;
 	(p6) addl r8 = 1, r0

opal/include/opal/sys/ia64/atomic.h

@@ -119,7 +119,7 @@ static inline int opal_atomic_cmpset_acq_64( volatile int64_t *addr,
     __asm__ __volatile__ ("cmpxchg8.acq %0=[%1],%2,ar.ccv":
                   "=r"(ret) : "r"(addr), "r"(newval) : "memory");
 
-    return ((int32_t)ret == oldval);
+    return (ret == oldval);
 }
 
 
@@ -132,7 +132,7 @@ static inline int opal_atomic_cmpset_rel_64( volatile int64_t *addr,
     __asm__ __volatile__ ("cmpxchg8.rel %0=[%1],%2,ar.ccv":
                   "=r"(ret) : "r"(addr), "r"(newval) : "memory");
 
-    return ((int32_t)ret == oldval);
+    return (ret == oldval);
 }
 
 #endif /* OMPI_GCC_INLINE_ASSEMBLY */