* sync opal_atomic_cmpset_{32,64} for AMD64 with the x86 32 bit version,

as I understand how that one works and don't really understand what
  was in the amd64 code (which was copied from before I started working
  on the inline assembly).  This fixes the race condition we were
  seeing on PGI causing test failures
* sync non-inline assembly with inline assembly version

This needs to go to the v1.0 branch

This commit was SVN r9539.

opal/asm/base/AMD64.asm

@@ -26,47 +26,20 @@ END_FUNC(opal_atomic_wmb)
 
 
 START_FUNC(opal_atomic_cmpset_32)
-	pushq	%rbp
+        movl    %esi, %eax
-	movq	%rsp, %rbp
+        lock; cmpxchgl %edx,(%rdi)   
-	movq	%rdi, -8(%rbp)
+        sete     %dl
-	movl	%esi, -12(%rbp)
+        movzbl  %dl, %eax
-	movl	%edx, -16(%rbp)
+        ret
-	movl	-16(%rbp), %ecx
-	movq	-8(%rbp), %rdx
-	movl	-12(%rbp), %eax
-	cmpxchgl %ecx,(%rdx)
-	movq	%rax, -24(%rbp)
-	movl	-24(%rbp), %eax
-	movl	%eax, -28(%rbp)
-	movl	-28(%rbp), %eax
-	cmpl	-12(%rbp), %eax
-	sete	%al
-	movzbl	%al, %eax
-	movl	%eax, -28(%rbp)
-	movl	-28(%rbp), %eax
-	leave
-	ret
 END_FUNC(opal_atomic_cmpset_32)
 
 
 START_FUNC(opal_atomic_cmpset_64)
-	pushq	%rbp
+        movq    %rsi, %rax
-	movq	%rsp, %rbp
+        lock; cmpxchgq %rdx,(%rdi)   
-	movq	%rdi, -8(%rbp)
+        sete     %dl
-	movq	%rsi, -16(%rbp)
+        movzbl  %dl, %eax
-	movq	%rdx, -24(%rbp)
+        ret
-	movq	-24(%rbp), %rcx
-	movq	-8(%rbp), %rdx
-	movq	-16(%rbp), %rax
-	cmpxchgq %rcx,(%rdx)   
-	
-	movq	%rax, -32(%rbp)
-	movq	-32(%rbp), %rax
-	cmpq	-16(%rbp), %rax
-	sete	%al
-	movzbl	%al, %eax
-	leave
-	ret
 END_FUNC(opal_atomic_cmpset_64)
 
 

opal/include/opal/sys/amd64/atomic.h

@@ -81,12 +81,15 @@ static inline void opal_atomic_wmb(void)
 static inline int opal_atomic_cmpset_32( volatile int32_t *addr,
                                         int32_t oldval, int32_t newval)
 {
-    unsigned long prev;
+   unsigned char ret;
-    __asm__ __volatile__(SMPLOCK "cmpxchgl %1,%2"
+   __asm__ __volatile (
-                         : "=a"(prev)
+                       SMPLOCK "cmpxchgl %1,%2   \n\t"
-                         : "q"(newval), "m"(*addr), "0"(oldval)
+                               "sete     %0      \n\t"
-                         : "cc", "memory");
+                       : "=qm" (ret)
-    return ((int32_t)prev == oldval);
+                       : "q"(newval), "m"(*((volatile long*)addr)), "a"(oldval)
+                       : "memory");
+
+   return (int)ret;
 }
 
 #endif /* OMPI_GCC_INLINE_ASSEMBLY */
@@ -99,15 +102,15 @@ static inline int opal_atomic_cmpset_32( volatile int32_t *addr,
 static inline int opal_atomic_cmpset_64( volatile int64_t *addr,
                                          int64_t oldval, int64_t newval)
 {
-   int64_t prev;
+   unsigned char ret;
-    
    __asm__ __volatile (
                        SMPLOCK "cmpxchgq %1,%2   \n\t"
-                       : "=a" (prev)
+                               "sete     %0      \n\t"
-                       : "q" (newval), "m" (*(addr)), "0"(oldval)
+                       : "=qm" (ret)
-                       : "cc", "memory");
+                       : "q"(newval), "m"(*((volatile long*)addr)), "a"(oldval)
+                       : "memory");
 
-   return (prev == oldval);
+   return (int)ret;
 }
 
 #endif /* OMPI_GCC_INLINE_ASSEMBLY */