* IA64 can have a weaker consistency model for memory than x86, so we

need memory barriers to actually do something other than hint
  to the compiler not to reorder memory-related instructions.  The
  IA64 instruction for memory barriers is "mf".

  Fixes bug #137.

This commit was SVN r10401.

opal/asm/base/IA64.asm

@@ -8,6 +8,7 @@ START_FILE
 opal_atomic_mb:
 	.prologue
 	.body
+	mf
 	br.ret.sptk.many b0
 	;;
 	.endp opal_atomic_mb#
@@ -17,6 +18,7 @@ opal_atomic_mb:
 opal_atomic_rmb:
 	.prologue
 	.body
+	mf
 	br.ret.sptk.many b0
 	;;
 	.endp opal_atomic_rmb#
@@ -26,6 +28,7 @@ opal_atomic_rmb:
 opal_atomic_wmb:
 	.prologue
 	.body
+	mf
 	br.ret.sptk.many b0
 	;;
 	.endp opal_atomic_wmb#

opal/include/opal/sys/ia64/atomic.h

@@ -24,11 +24,7 @@
  */
 
 
-#if OMPI_WANT_SMP_LOCKS
-#define MB() __asm__ __volatile__("": : :"memory")
-#else
-#define MB()
-#endif
+#define MB() __asm__ __volatile__("mf": : :"memory")
 
 
 /**********************************************************************