139 строки
2.2 KiB
C
139 строки
2.2 KiB
C
/*
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* (c) 2024, SWD Embedded Systems Limited, http://www.kpda.ru
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*/
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#ifndef _SUNXI_PLATFORM_H_INCLUDED
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#define _SUNXI_PLATFORM_H_INCLUDED
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/*
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* CLK IDs
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*/
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/* CCU CLK IDs */
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enum sunxi_clk_index {
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THS_CLK,
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NAND0_CLK,
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NAND1_CLK,
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SDMMC0_CLK,
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SDMMC1_CLK,
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SDMMC2_CLK,
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SDMMC3_CLK,
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TS_CLK,
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SS_CLK,
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SPI0_CLK,
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SPI1_CLK,
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SPI2_CLK,
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SPI3_CLK,
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I2S0_CLK,
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I2S1_CLK,
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I2S2_CLK,
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TDM_CLK,
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OWA_CLK,
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KEYPAD_CLK,
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SATA_CLK,
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USB_CLK,
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CIR0_CLK,
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CIR1_CLK,
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EMAC_CLK,
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EPHY_CLK,
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DRAM_CLK,
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DE_CLK,
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DE_MP_CLK,
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BE0_CLK,
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BE1_CLK,
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FE0_CLK,
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FE1_CLK,
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MP_CLK,
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LCD0_TCON_CLK,
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LCD1_TCON_CLK,
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TV0_TCON_CLK,
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TV1_TCON_CLK,
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TCON0_CH0_CLK,
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TCON1_CH0_CLK,
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TVE0_CLK,
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TVE1_CLK,
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DEINTERLACE_CLK,
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TCON0_CH1_CLK,
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TCON1_CH1_CLK,
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CSI_MISC_CLK,
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CSI0_CLK,
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CSI1_CLK,
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VE_CLK,
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ADDA_CLK,
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AVS_CLK,
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DMIC_CLK,
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HDMI0_CLK,
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HDMI1_CLK,
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HDMI_SLOW_CLK,
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PS_CLK,
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MTC_CLK,
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MBUS0_CLK,
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MBUS1_CLK,
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GMAC_CLK,
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MIPI_DSI_CLK,
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MIPI_CSI_CLK,
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IEP_DRC0_CLK,
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IEP_DRC1_CLK,
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IEP_DEU0_CLK,
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IEP_DEU1_CLK,
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TVD0_CLK,
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TVD1_CLK,
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TVD2_CLK,
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TVD3_CLK,
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GPU_CLK,
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GPU_MEM_CLK,
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GPU_HYD_CLK,
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ATS_CLK,
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TRACE_CLK,
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CLK_OUTA,
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CLK_OUTB,
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CCU_CLK_MAX,
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} sunxi_clk_index;
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/* CCU PLL IDs */
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enum sunxi_pll_clocks {
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PLL_CPU0_CTRL = CCU_CLK_MAX,
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PLL_CPU1_CTRL,
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PLL_AUDIO_CTRL,
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PLL_VIDEO0_CTRL,
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PLL_VIDEO1_CTRL,
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PLL_VE_CTRL,
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PLL_DDR0_CTRL,
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PLL_DDR1_CTRL,
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PLL_PERIPH0_CTRL,
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PLL_PERIPH1_CTRL,
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PLL_GPU_CTRL,
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PLL_DE_CTRL,
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PLL_SATA_CTRL,
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PLL_MIPI_CTRL,
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CCU_PLL_MAX,
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} sunxi_pll_clocks;
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/* CCU CLK PARENT IDs */
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enum sunxi_clk_parent {
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OSC_24M = CCU_PLL_MAX,
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PLL_AUDIO,
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PLL_AUDIO_2X,
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PLL_AUDIO_4X,
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PLL_AUDIO_8X,
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PLL_VIDEO0,
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PLL_VIDEO0_2X,
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PLL_VIDEO1,
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PLL_VIDEO1_2X,
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PLL_VE,
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PLL_DDR0,
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PLL_DDR1,
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PLL_PERIPH0,
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PLL_PERIPH0_2X,
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PLL_GPU,
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PLL_PERIPH1,
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PLL_PERIPH1_2X,
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PLL_DE,
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PLL_SATA,
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PLL_MIPI,
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CLK_PARENT_MAX,
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} sunxi_clk_parent;
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#endif /* _SUNXI_PLATFORM_H_INCLUDED */
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