299 строки
8.5 KiB
C
299 строки
8.5 KiB
C
/*
|
|
* (c) 2024, SWD Embedded Systems Limited, http://www.kpda.ru
|
|
*/
|
|
|
|
#ifndef _SUN8IW7_PLATFORM_H_INCLUDED
|
|
#define _SUN8IW7_PLATFORM_H_INCLUDED
|
|
|
|
#include <errno.h>
|
|
#include <sunxi.h>
|
|
#include <clock.h>
|
|
|
|
/*
|
|
* SUN8IW7
|
|
* Converting functions of register's
|
|
*/
|
|
static inline int sun8iw7_convert_clk_index(enum sunxi_clk_index id, int *clk_shift)
|
|
{
|
|
int res = (EOK);
|
|
|
|
switch(id)
|
|
{
|
|
case THS_CLK: *clk_shift = 0x00; break;
|
|
case NAND0_CLK: *clk_shift = 0x03; break;
|
|
case SDMMC0_CLK: *clk_shift = 0x05; break;
|
|
case SDMMC1_CLK: *clk_shift = 0x06; break;
|
|
case SDMMC2_CLK: *clk_shift = 0x07; break;
|
|
case SS_CLK: *clk_shift = 0x0A; break;
|
|
case SPI0_CLK: *clk_shift = 0x0B; break;
|
|
case SPI1_CLK: *clk_shift = 0x0C; break;
|
|
case I2S0_CLK: *clk_shift = 0x0F; break;
|
|
case I2S1_CLK: *clk_shift = 0x10; break;
|
|
case I2S2_CLK: *clk_shift = 0x11; break;
|
|
case OWA_CLK: *clk_shift = 0x13; break;
|
|
case DE_CLK: *clk_shift = 0x24; break;
|
|
case LCD0_TCON_CLK: *clk_shift = 0x29; break;
|
|
case LCD1_TCON_CLK: *clk_shift = 0x2A; break;
|
|
case TVE0_CLK: *clk_shift = 0x2B; break;
|
|
case DEINTERLACE_CLK: *clk_shift = 0x2C; break;
|
|
case CSI_MISC_CLK: *clk_shift = 0x2F; break;
|
|
case CSI0_CLK: *clk_shift = 0x30; break;
|
|
case VE_CLK: *clk_shift = 0x32; break;
|
|
case ADDA_CLK: *clk_shift = 0x33; break;
|
|
case AVS_CLK: *clk_shift = 0x34; break;
|
|
case HDMI0_CLK: *clk_shift = 0x37; break;
|
|
case HDMI_SLOW_CLK: *clk_shift = 0x38; break;
|
|
case MBUS0_CLK: *clk_shift = 0x39; break;
|
|
case GPU_CLK: *clk_shift = 0x4B; break;
|
|
case EMAC_CLK: *clk_shift = (-ENOTSUP); break;
|
|
case EPHY_CLK: *clk_shift = (-ENOTSUP); break;
|
|
|
|
default: res = EPERM;
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
static inline int sun8iw7_convert_pll_index(enum sunxi_pll_clocks id, int *pll_shift)
|
|
{
|
|
int res = (EOK);
|
|
|
|
switch(id)
|
|
{
|
|
case PLL_CPU0_CTRL: *pll_shift = 0x00; break;
|
|
case PLL_AUDIO_CTRL: *pll_shift = 0x02; break;
|
|
case PLL_VIDEO0_CTRL: *pll_shift = 0x04; break;
|
|
case PLL_VE_CTRL: *pll_shift = 0x06; break;
|
|
case PLL_DDR0_CTRL: *pll_shift = 0x08; break;
|
|
case PLL_PERIPH0_CTRL: *pll_shift = 0x0A; break;
|
|
case PLL_GPU_CTRL: *pll_shift = 0x0E; break;
|
|
case PLL_PERIPH1_CTRL: *pll_shift = 0x11; break;
|
|
case PLL_DE_CTRL: *pll_shift = 0x12; break;
|
|
|
|
default: res = EPERM; break;
|
|
}
|
|
|
|
return (res);
|
|
}
|
|
|
|
static inline int sun8iw7_check_clk_parent_index(enum sunxi_clk_parent id)
|
|
{
|
|
switch (id)
|
|
{
|
|
case PLL_AUDIO_8X:
|
|
case PLL_AUDIO_4X:
|
|
case PLL_AUDIO_2X:
|
|
case PLL_AUDIO:
|
|
case PLL_VIDEO0:
|
|
case PLL_VE:
|
|
case PLL_PERIPH0:
|
|
case PLL_PERIPH0_2X:
|
|
case PLL_PERIPH1:
|
|
case PLL_DDR0:
|
|
case PLL_DE:
|
|
return (EOK);
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
}
|
|
|
|
static inline uint8_t sun8iw7_get_struct_bus_gating(enum sunxi_clk_index id, uint8_t *num_bus)
|
|
{
|
|
/* BUS_CLK_GATING_REG0 */
|
|
*num_bus = 0;
|
|
switch (id)
|
|
{
|
|
case SS_CLK: return 5;
|
|
case SDMMC0_CLK: return 8;
|
|
case SDMMC1_CLK: return 9;
|
|
case SDMMC2_CLK: return 10;
|
|
case NAND0_CLK: return 13;
|
|
case DRAM_CLK: return 14;
|
|
case EMAC_CLK: return 17;
|
|
case TS_CLK: return 18;
|
|
case SPI0_CLK: return 20;
|
|
case SPI1_CLK: return 21;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_CLK_GATING_REG1 */
|
|
*num_bus = 1;
|
|
switch (id)
|
|
{
|
|
case VE_CLK: return 0;
|
|
case LCD0_TCON_CLK: return 3;
|
|
case LCD1_TCON_CLK: return 4;
|
|
case DEINTERLACE_CLK: return 5;
|
|
case CSI0_CLK: return 8;
|
|
case TVE0_CLK: return 9;
|
|
case HDMI_SLOW_CLK: return (-ENOTSUP);
|
|
case HDMI0_CLK: return 11;
|
|
case DE_CLK: return 12;
|
|
case GPU_CLK: return 20;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_CLK_GATING_REG2 */
|
|
*num_bus = 2;
|
|
switch (id)
|
|
{
|
|
case ADDA_CLK: return 0;
|
|
case OWA_CLK: return 1;
|
|
case THS_CLK: return 8;
|
|
case I2S0_CLK: return 12;
|
|
case I2S1_CLK: return 13;
|
|
case I2S2_CLK: return 14;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_CLK_GATING_REG3 */
|
|
*num_bus = 3;
|
|
switch (id)
|
|
{
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_CLK_GATING_REG4 */
|
|
*num_bus = 4;
|
|
switch (id)
|
|
{
|
|
case EPHY_CLK: return 0;
|
|
default: break;
|
|
}
|
|
|
|
return (ENOTSUP);
|
|
}
|
|
|
|
static inline uint8_t sun8iw7_get_struct_bus_sft_rst(enum sunxi_clk_index id, uint8_t *num_bus)
|
|
{
|
|
/* BUS_SOFT_RST_REG0 */
|
|
*num_bus = 0;
|
|
switch (id)
|
|
{
|
|
case SS_CLK: return 5;
|
|
case SDMMC0_CLK: return 8;
|
|
case SDMMC1_CLK: return 9;
|
|
case SDMMC2_CLK: return 10;
|
|
case NAND0_CLK: return 13;
|
|
case DRAM_CLK: return 14;
|
|
case EMAC_CLK: return 17;
|
|
case TS_CLK: return 18;
|
|
case SPI0_CLK: return 20;
|
|
case SPI1_CLK: return 21;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_SOFT_RST_REG1 */
|
|
*num_bus = 1;
|
|
switch (id)
|
|
{
|
|
case VE_CLK: return 0;
|
|
case LCD0_TCON_CLK: return 3;
|
|
case LCD1_TCON_CLK: return 4;
|
|
case DEINTERLACE_CLK: return 5;
|
|
case CSI0_CLK: return 8;
|
|
case TVE0_CLK: return 9;
|
|
case HDMI_SLOW_CLK: return 10;
|
|
case HDMI0_CLK: return 11;
|
|
case DE_CLK: return 12;
|
|
case GPU_CLK: return 20;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_SOFT_RST_REG2 */
|
|
*num_bus = 2;
|
|
switch (id)
|
|
{
|
|
case EPHY_CLK: return 2;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_SOFT_RST_REG3 */
|
|
*num_bus = 3;
|
|
switch (id)
|
|
{
|
|
case ADDA_CLK: return 0;
|
|
case OWA_CLK: return 1;
|
|
case THS_CLK: return 8;
|
|
case I2S0_CLK: return 12;
|
|
case I2S1_CLK: return 13;
|
|
case I2S2_CLK: return 14;
|
|
default: break;
|
|
}
|
|
|
|
/* BUS_SOFT_RST_REG4 */
|
|
*num_bus = 4;
|
|
switch (id)
|
|
{
|
|
default: break;
|
|
}
|
|
|
|
return (ENOTSUP);
|
|
}
|
|
|
|
static inline int sun8iw7_covert_clk_parent_to_pll_ctrl(enum sunxi_clk_parent id, enum sunxi_pll_clocks *pll_id)
|
|
{
|
|
/*
|
|
* x - is the coefficient of pll
|
|
* if x < 0 - is a division
|
|
* if x > 0 - is a multiplication
|
|
*/
|
|
|
|
int x = 1;
|
|
|
|
switch (id)
|
|
{
|
|
case PLL_AUDIO: x = -8; goto set_audio_pll;
|
|
case PLL_AUDIO_2X: x = -4; goto set_audio_pll;
|
|
case PLL_AUDIO_4X: x = -2;
|
|
case PLL_AUDIO_8X:
|
|
set_audio_pll:
|
|
*pll_id = PLL_AUDIO_CTRL;
|
|
break;
|
|
case PLL_VIDEO0_2X: x = 2;
|
|
case PLL_VIDEO0:
|
|
*pll_id = PLL_VIDEO0_CTRL;
|
|
break;
|
|
case PLL_VE:
|
|
*pll_id = PLL_VE_CTRL;
|
|
break;
|
|
case PLL_PERIPH0: x = -2;
|
|
case PLL_PERIPH0_2X:
|
|
*pll_id = PLL_PERIPH0_CTRL;
|
|
break;
|
|
case PLL_PERIPH1:
|
|
*pll_id = PLL_PERIPH0_CTRL;
|
|
break;
|
|
case PLL_DDR0:
|
|
*pll_id = PLL_DDR0_CTRL;
|
|
break;
|
|
case PLL_DE:
|
|
*pll_id = PLL_DE_CTRL;
|
|
break;
|
|
case OSC_24M:
|
|
*pll_id = OSC24M; // 24MHz
|
|
break;
|
|
default:
|
|
return (-ENOTSUP);
|
|
}
|
|
|
|
return x;
|
|
}
|
|
|
|
static inline plat_func_t sun8iw7_get_plat_func(void)
|
|
{
|
|
const static plat_func_t func =
|
|
{
|
|
.convert_clk_index = sun8iw7_convert_clk_index,
|
|
.convert_pll_index = sun8iw7_convert_pll_index,
|
|
.check_clk_parent_index = sun8iw7_check_clk_parent_index,
|
|
.get_struct_bus_gat = sun8iw7_get_struct_bus_gating,
|
|
.get_struct_bus_rst = sun8iw7_get_struct_bus_sft_rst,
|
|
.covert_clk_parent_to_pll_ctrl = sun8iw7_covert_clk_parent_to_pll_ctrl,
|
|
};
|
|
|
|
return func;
|
|
}
|
|
|
|
#endif /* _SUN8IW7_PLATFORM_H_INCLUDED */
|