197 строки
8.6 KiB
C
197 строки
8.6 KiB
C
/*
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* (c) 2020, SWD Embedded Systems Limited, http://www.kpda.ru
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*/
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/*************************************************/
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/* COMMON REGISTERS */
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/* Elvees 1892VM14YA ARMv7 SoC (VPOUT DC) */
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/*************************************************/
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/*************************************************/
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/* Registers base */
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/*************************************************/
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/* Synchronization interface controller (CMCTR) */
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#define CMCTR_REGISTERS_BASE 0x38094000
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#define CMCTR_REGISTERS_SIZE 0x1000
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/* GPIO interface */
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#define GPIO_REGISTERS_SIZE 0x1000
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/*************************************************/
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/* Registers interface */
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/*************************************************/
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/* Common registers interface */
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#define MMIO64( offset ) ((volatile uint64_t *)(vpout_draw->registers + (offset)))
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#define MMIO32( offset ) ((volatile uint32_t *)(vpout_draw->registers + (offset)))
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/* CMCTR registers interface */
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#define CMCTR_MMIO64( offset ) ((uint64_t *)(vpout->cmctr_registers + (offset)))
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#define CMCTR_MMIO32( offset ) ((uint32_t *)(vpout->cmctr_registers + (offset)))
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/* GPIO registers interface */
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#define GPIO_MMIO64( base, offset ) ((uint64_t *)(base + (offset)))
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#define GPIO_MMIO32( base, offset ) ((uint32_t *)(base + (offset)))
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/*************************************************/
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/* Display (LCD) controller registers */
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/*************************************************/
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#define LCDCSR (0x00) /* LCD control and status */
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#define CSR_CLR (1 << 3)
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#define CSR_INIT (1 << 2)
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#define CSR_RUN (1 << 1)
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#define CSR_EN (1 << 0)
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#define LCDDIV (0x04) /* ACLK pixel clock divider */
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#define LCDMODE (0x08)
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#define LCDMODE_CLK_ON (1 << 17)
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#define LCDMODE_VDEF (1 << 16)
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#define LCDMODE_HDEF (1 << 15)
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#define LCDMODE_DEN_EN (1 << 14)
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#define LCDMODE_INSYNC (1 << 13)
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#define LCDMODE_CCM (1 << 12)
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#define LCDMODE_PINV (1 << 11)
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#define LCDMODE_DINV (1 << 10)
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#define LCDMODE_VINV (1 << 9)
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#define LCDMODE_HINV (1 << 8)
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#define LCDMODE_BUF_NUMB (1 << 7)
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#define LCDMODE_BUF_MODE (1 << 6)
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#define LCDMODE_HWC_MODE (1 << 5) /* Hardware cursor mode */
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#define LCDMODE_HWC_MODE_32x32 (0 << 5)
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#define LCDMODE_HWC_MODE_64x64 (1 << 5)
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#define LCDMODE_HWCEN (1 << 4) /* Enable hardware cursor */
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#define LCDMODE_INSIZE (0xf << 0)
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#define LCDMODE_INSIZE_RGB332 (0 << 0)
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#define LCDMODE_INSIZE_RGB444 (1 << 0)
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#define LCDMODE_INSIZE_ARGB1555 (2 << 0)
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#define LCDMODE_INSIZE_RGB565 (3 << 0)
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#define LCDMODE_INSIZE_18bpp (4 << 0)
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#define LCDMODE_INSIZE_RGB888 (5 << 0)
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#define LCDMODE_INSIZE_ARGB8888 (6 << 0)
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#define LCDMODE_INSIZE_INDEXED_1BIT (8 << 0)
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#define LCDMODE_INSIZE_INDEXED_2BIT (9 << 0)
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#define LCDMODE_INSIZE_INDEXED_4BIT (10 << 0)
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#define LCDMODE_INSIZE_INDEXED_8BIT (11 << 0)
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#define LCDHT0 (0x0c) /* LCD horizontal timings */
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#define LCDHT0_HGDEL_MASK (0xffff << 16)
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#define LCDHT0_HGDEL_SHIFT (16)
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#define LCDHT0_HSW_MASK (0xffff << 0)
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#define LCDHT0_HSW_SHIFT (0)
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#define LCDHT1 (0x10) /* LCD horizontal timings */
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#define LCDHT1_HLEN_MASK (0xffff << 16)
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#define LCDHT1_HLEN_SHIFT (16)
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#define LCDHT1_HGATE_MASK (0xffff << 0)
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#define LCDHT1_HGATE_SHIFT (0)
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#define LCDVT0 (0x14) /* LCD vertical timings */
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#define LCDHT1_VGDEL_MASK (0xffff << 16)
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#define LCDHT1_VGDEL_SHIFT (16)
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#define LCDHT1_VSW_MASK (0xffff << 0)
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#define LCDHT1_VSW_SHIFT (0)
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#define LCDVT1 (0x18) /* LCD vertical timings */
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#define LCDHT1_VLEN_MASK (0xffff << 16)
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#define LCDHT1_VLEN_SHIFT (16)
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#define LCDHT1_VGATE_MASK (0xffff << 0)
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#define LCDHT1_VGATE_SHIFT (0)
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#define LCDXY (0x1c)
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#define LCDXYP (0x20)
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#define LCDCOLOR0 (0x24)
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#define LCDCOLOR1 (0x28)
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#define LCDAB0 (0x2c) /* LCD primary buffer address */
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#define LCDAB1 (0x30) /* LCD secondary buffer address */
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#define LCDOF0 (0x34) /* LCD primary buffer stride (64b aligned) */
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#define LCDOF1 (0x38) /* LCD secondary buffer stride (64b aligned) */
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#define LCDINT (0x44) /* LCD interrupt control */
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#define LCDINTMASK (0x48) /* LCD interrupt mask */
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#define INTERRUPT_SYNC_DONE (1 << 5) /* VSYNC IRQ */
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#define INTERRUPT_OUT_FIFO_EMPTY (1 << 3)
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#define INTERRUPT_OUT_FIFO (1 << 2)
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#define INTERRUPT_DMA_FIFO_EMPTY (1 << 1)
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#define INTERRUPT_DMA_DONE (1 << 0)
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#define HWC_MEM (0x400)
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#define PAL_MEM (0x800) /* Palette memory offset */
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/*************************************************/
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/* CMCTR registers */
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/*************************************************/
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#define GATE_CORE_CTR (0x48) /* Frequency disable register for CMCTR_CORE */
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#define VPOUT_EN (1 << 4) /* Frequency enable bit for VPOUT, VPOUT_PCLK, VPOUT_ACLK */
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#define SEL_CPLL (0x104) /* CPLL control register */
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#define SEL_CPLL_LOCK (1 << 31)
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#define SEL_CPLL_SEL (0xff << 0)
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#define SEL_SPLL (0x10c) /* SPLL control register */
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#define SEL_SPLL_LOCK (1 << 31)
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#define SEL_SPLL_SEL (0xff << 0)
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/*************************************************/
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/* GPIO registers */
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/*************************************************/
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#define GPIO_SWPORTA_DR (0x00)
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#define GPIO_SWPORTB_DR (0x0C)
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#define GPIO_SWPORTC_DR (0x18)
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#define GPIO_SWPORTD_DR (0x24)
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#define GPIO_SWPORTA_DDR (0x04)
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#define GPIO_SWPORTB_DDR (0x10)
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#define GPIO_SWPORTC_DDR (0x1C)
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#define GPIO_SWPORTD_DDR (0x28)
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#define GPIO_SWPORTA_CTL (0x08)
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#define GPIO_SWPORTB_CTL (0x14)
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#define GPIO_SWPORTC_CTL (0x20)
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#define GPIO_SWPORTD_CTL (0x2C)
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/*************************************************/
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/* ITE IT66121 I2C HDMI controller registers */
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/*************************************************/
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#define REG_RESET (0x04)
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#define RESET_RCLK_MASK (1 << 5)
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#define RESET_AUDIO_MASK (1 << 4)
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#define RESET_VIDEO_MASK (1 << 3)
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#define RESET_AFIFO_MASK (1 << 2)
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#define RESET_HDCP_MASK (1 << 0)
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#define REG_IRQ_FIRST (0x09)
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#define REG_IRQ_LAST (0x0B)
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#define REG_BANK_SW (0x0F)
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#define REG_TX_RESET (0x61)
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#define REG_CLK1 (0x62)
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#define REG_CLK2 (0x63)
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#define REG_CLK3 (0x64)
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#define REG_TXFIFO_SET (0x71)
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#define REG_AVMUTE (0xC1)
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