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BSP для ЗОСРВ "Нейтрино" редакции 2021

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58
Makefile Обычный файл
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# This is the top level Makefile for all source packages.
# It makes all the code in the "src" directory, then installs it
# to the "install" directory", then makes the images in
# the images directory (if present)
ROOT_DIR := $(notdir $(CURDIR))
ifndef QCONFIG
QCONFIG=qconfig.mk
endif
include $(QCONFIG)
unexport ROOT_DIR
.PHONY: all install clean make_builds clean_builds dummy images prebuilt
# Expands to a single newline character
define NEWLINE
endef
SUFFIXES := .mk
all:
$(if $(wildcard prebuilt/*), $(MAKE) prebuilt)
$(if $(wildcard src/*), $(MAKE) -Csrc hinstall)
$(if $(wildcard src/*), $(MAKE) -Csrc install)
$(MAKE) make_builds
$(MAKE) images
@echo done
subdirs:=$(subst /Makefile,,$(wildcard */[Mm]akefile))
clean:
$(foreach dir,$(subdirs), $(MAKE) -C$(dir) clean $(NEWLINE))
-$(RM_HOST) -rv install/*
install: all
make_builds:
@$(foreach file,$(wildcard install/*/boot/build/*), \
$(if $(wildcard images/$(notdir $(file))), \
echo Skip $(wildcard images/$(notdir $(file))), \
echo Copy $(file) to images/$(notdir $(file)); $(CP_HOST) -n $(file) images/$(notdir $(file)));)
clean_builds:
@$(if $(wildcard install/*/boot/build/*), \
$(foreach file,$(wildcard install/*/boot/build/*), \
echo Delete images/$(notdir $(file)); $(RM_HOST) images/$(notdir $(file)); ), \
$(foreach file,$(wildcard prebuilt/*/boot/build/*), \
echo Delete images/$(notdir $(file)); $(RM_HOST) images/$(notdir $(file)); ))
images:
$(if $(wildcard images/*.build), $(MAKE) -Cimages)
prebuilt:
-$(RM_HOST) -rf install/*
$(CP_HOST) -r prebuilt/* install/

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# BSP для платы OrangePi PC на базе Allwinner H3 (ARMv7 Cortex-A7 QuadCore)
## Руководство пользователя и бинарная сборка
- [Бинарный релиз](https://git.kpda.ru/BSP/kpda-bsp-allwinner-h3-orangepipc/releases/tag/release-2021)
- [Руководство пользователя](https://git.kpda.ru/BSP/kpda-bsp-allwinner-h3-orangepipc/releases/download/release-2021/UserManual.pdf)
## Поддерживаемые редакции
- 2021
- 2020 (ограниченно)
## Сборка BSP
Скопировать BSP в рабочую директорию
Сменить текущую директорию на директорию с BSP
`cd kpda-bsp-allwinner-h3-orangepipc`
Для сборки образа из файла построения orangepi.build
`make -j$(nproc)`
## Передача образа на плату
- скопировать полученный образ в папку tftp-сервера;
`tftp -R 6969:6969 172.16.x.x -c put ifs-h3-orangepi.bin ifs-h3-orangepi.bin`
- подключить плату по usb-uart;
- проверить наличие устройства /dev/ttyUSB0;
- настроить minicom со следующими параметрами: скорость 115200, 8 бит, без контроля
четности, 1 стоп-бит, порт /dev/ttyUSB0;
- запустить minicom и включить плату;
- после запуска U-Boot ввести следующую последовательность команд:
Установка ip-адреса для модуля:
`=> setenv ipaddr 172.16.x.x`
Установка ip-адреса для tftp-сервера:
`=> setenv serverip 172.16.x.x`
`=> setenv gatewayip 172.16.x.x`
Загрузка
```
=> tftpboot 0x41000000 ifs-h3-orangepi.bin
=> go 0x41000000
```
Пример скрипта `tftp.sh` для автоматизации:
```
#!/bin/bash
set -ex
TFTP_SERIAL=${TTY_SERIAL:-/dev/ttyUSB0}
TFTP_CLIENT=172.16.x.x
TFTP_SERVER=172.16.x.x
image="ifs-h3-orangepi.bin"
tftp -R 6969:6969 $TFTP_SERVER -c put $image $image
echo "setenv ipaddr $TFTP_CLIENT" > $TFTP_SERIAL
echo "setenv serverip $TFTP_SERVER" > $TFTP_SERIAL
echo "setenv gatewayip $TFTP_SERVER" > $TFTP_SERIAL
echo "tftpboot 0x41000000 $image; go 0x41000000" > $TFTP_SERIAL
```
Запуск:
`./tftp.sh`
## Поддерживаемые компоненты
| Компонент | Поддержка | Протестировано | Комментарий |
| :------------: | :-------: | :------------: | :----------------------------------------------------: |
| RAM | 1GB | + | |
| SMP | 4 CPU cores | + | |
| UART | + | + | |
| NET | + | + | |

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docs/00-UserGuide.dox Обычный файл
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@page "00-UserGuide" BSP для OrangePi-PC Allwinner-H3
@par Аннотация
@brief Данный документ представляет собой руководство пользователя для пакета поддержки платы OrangePi-PC на основе интегральной микросхемы Allwinner-H3 под ЗОСРВ «Нейтрино».
Процессорная архитектура: ARMv7 Little Endian
@hide @arch{armv7} @endhide
Поддерживаемые устройства:
- Одноплатный компьютер @link{http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-PC.html}OrangePi-PC@endlink
Документ включает следующие разделы:
@ul
@item Основные термины и сокращения
@item Общие сведения
@item Состав и структура
@item Установка и настройка
@item Загрузка образа ОС
@item Описание компонентов
@item Проверка функционирования
@item Известные особенности
@item Журнал изменений
@endul
В разделе «Основные термины и сокращения» приведена расшифровка сокращений, используемых в данном документе.
В разделе «Общие сведения» приведены назначение и функции ППМ, а также описание используемых технических средств.
В разделе «Состав и структура» приведены сведения о структуре ППМ, его составных частях и назначении составных частей.
В разделе «Установка и настройка» приведены указания по установке и настройке компонентов сред разработки и сред исполнения, необходимых для функционирования ППМ и сборки загружаемого образа ЗОСРВ «Нейтрино».
В разделе «Загрузка образа ОС» приведены сведения о вариантах запуска загружаемого образа ЗОСРВ «Нейтрино» на целевой системе.
В разделе «Описание компонентов» приведены описания компонентов ППМ.
В разделе «Проверка функционирования» приведены указания по проверке работоспособности пакета поддержки.
В разделе «Известные особенности» приведены известные особбености и ограничения текущей версии пакета поддержки.
@group table_of_articles
@@table[width:40:60:width] Раздел @| Описание

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@page "Glossary" Основные термины и сокращения
@brief Основные термины и сокращения, используемые в данном руководстве
@dl
@term ЗОСРВ
@use защищенная операционная система реального времени
@term ПМ
@use процессорный модуль
@term ППМ
@term BSP
@use пакет поддержки микропроцессора
@enddl
@prev{./00-UserGuide.html|table_of_articles||1}

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@page "GeneralInfo" Общие сведения
@brief Общие сведения
@br
Пакет поддержки платы OrangePi-PC (ППМ) предназначен для обеспечения запуска и функционирования ЗОСРВ «Нейтрино» на процессорном модуле (ПМ) на на основе интегральной микросхемы Allwinner-H3.
@br
Для работы с ППМ необходим инструментальный ПК с установленным комплектом разработчика для ЗОСРВ «Нейтрино» в варианте _Linux Host_ и целевая плата OrangePi-PC на основе интегральной микросхемы Allwinner-H3.
@br
ППМ совместим со следующими редакциями ЗОСРВ «Нейтрино»: @b 2021, @b 2020 (ограниченно).
@br
ППМ обеспечивает поддержку и функционирование следующих блоков и интерфейсов интегральной микросхемы Allwinner-H3:
@ul
@item процессорнные ядра Cortex-A7 в режиме SMP
@item контроллер прерываний GICv2
@item контроллер оперативной памяти DDR
@item UART
@item Ethernet
@endul
@prev{./00-UserGuide.html|table_of_articles||2}

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@page "Contents" Состав и структура
@brief Состав и структура
@br
ППМ представляет собой архив, имеющий формат .tar.gz и имя вида «kpda-bsp-allwinner-h3-orangepipc-(версия-ОС)-(формат)-(дата)-(хэш-git).tar.gz».
Назначение полей:
@ul
@item (версия-ОС) - версия ЗОСРВ для которой предназначен BSP
@item (формат) - формат ППМ: @a src для версии с исходными кодами, @a bin для версии с бинарными компонентами
@item (дата) - дата сборки и запаковки BSP в формате ГГГГММДД
@item (хэш-git) - номер или хэш коммита системы контроля версией git
@endul
@br
Архив ППМ содержит следующие компоненты:
@output{asciiart}
kpda-bsp-allwinner-h3-orangepipc/ # Каталог верхнего уровня
|--> images/ # Каталог с загрузочным образом (IFS) и файлами построения
| |--> ifs-h3-orangepi.bin # Загружаемый образ ЗОСРВ «Нейтрино»
| `--> *.build # Файлы построения загрузочных образов
|--> install/ # Бинарные компоненты, собираемые из исходных кодов
| `--> usr/include/ # Заголовочные файлы
`--> src/ # Исходные коды компонентов ППМ
@endoutput
@prev{./00-UserGuide.html|table_of_articles||3}

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@page "Install" Установка и настройка
@brief Установка и настройка
@br
Распаковывать архив с ППМ следует на инструментальной машине @a x86_64 c ОС @a Linux с установленным комплектом разработчика ЗОСРВ «Нейтрино».
Для распаковки ППМ следует скопировать архив в рабочий каталог и выполнить команду:
@output{shell}
$ tar xzf kpda-bsp-allwinner-h3-orangepipc-*.tar.gz
@endoutput
Для сборки ППМ выполните следующие команды:
@output{shell}
$ cd kpda-bsp-allwinner-h3-orangepipc
$ make
@endoutput
В результате будет произведена сборка ППМ и подготовлен загрузочный образ ЗОСРВ «Нейтрино» @c ifs-h3-orangepi.bin.
@prev{./00-UserGuide.html|table_of_articles||4}

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@page "Boot" Загрузка образа ОС
@brief Загрузка образа ОС
@@item Загрузка образа по сети
@@item Загрузка образа с SD карты памяти
@@item Результат загрузки образа
@@item Сохранение варианта загрузки по-умолчанию
@group boot_net
Для загрузки образа ЗОСРВ «Нейтрино» на ПМ по сети используется протокол TFTP. На инструментальной системе необходимо настроить TFTP сервер и скопировать полученный загрузочный образ @c ifs-h3-orangepi.bin в каталог, использующийся TFTP сервером.
@br
Затем следует подключить отладочный USB-UART ПМ к USB порту инструментального ПК, проверить наличие устройства `/dev/ttyUSB*` и запустить терминальную программу, например, minicom со следующими параметрами: скорость 115200, 8 бит, без контроля четности, 1 стоп-бит, порт `/dev/ttyUSB0`.
@br
После включения питания ПМ в терминальной программе должен присутствовать отладочный вывод загрузчика U-Boot. Например:
@output{shell}
U-Boot SPL 2020.04-orangepi (Oct 26 2020 - 16:27:23 +0800)
DRAM: 1024 MiB
Trying to boot from MMC1
U-Boot 2020.04-orangepi (Oct 26 2020 - 16:27:23 +0800) Allwinner Technology
CPU: Allwinner H3 (SUN8I 1680)
Model: Xunlong Orange Pi PC
DRAM: 1 GiB
MMC: mmc@1c0f000: 0
Loading Environment from FAT... Unable to use mmc 0:1... In: serial@1c28000
Out: serial@1c28000
Err: serial@1c28000
Net: phy interface0
eth0: ethernet@1c30000
starting USB...
Bus usb@1c1a000: USB EHCI 1.00
Bus usb@1c1a400: USB OHCI 1.0
Bus usb@1c1b000: USB EHCI 1.00
Bus usb@1c1b400: USB OHCI 1.0
Bus usb@1c1c000: USB EHCI 1.00
Bus usb@1c1c400: USB OHCI 1.0
Bus usb@1c1d000: USB EHCI 1.00
Bus usb@1c1d400: USB OHCI 1.0
scanning bus usb@1c1a000 for devices... 1 USB Device(s) found
scanning bus usb@1c1a400 for devices... 1 USB Device(s) found
scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
scanning bus usb@1c1b400 for devices... 1 USB Device(s) found
scanning bus usb@1c1c000 for devices... 1 USB Device(s) found
scanning bus usb@1c1c400 for devices... 1 USB Device(s) found
scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
scanning bus usb@1c1d400 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Autoboot in 1 seconds, press <Space> to stop
=>
@endoutput
@br
Для загрузки образа ЗОСРВ «Нейтрино» cледует остановить загрузку и в консоли загрузчика U-Boot выполнить следующие команды:
@ul
@item Указать IP-адрес TFTP сервера:
@output{shell}
=> setenv serverip 172.16.0.16
=> setenv gatewayip 172.16.0.16
@endoutput
@item Установить IP-адрес модулю, для организации обмена по протоколу TFTP:
@output{shell}
=> setenv ipaddr 172.16.10.44
@endoutput
@item Загрузить образ по протоколу TFTP и запустить его:
@output{shell}
=> tftpboot 0x41000000 ifs-h3-orangepi.bin
=> go 0x41000000
@endoutput
@endul
@group boot_sd
Для загрузки образа ЗОСРВ «Нейтрино» с карты памяти SD/microSD, скопируйте заранее подготовленный загрузочный образ @c ifs-h3-orangepi.bin на FAT раздел карты памяти и после включения питания ПМ в консоли загрузчика U-Boot выполните следующие команды:
@output{shell}
=> fatload mmc 0 0x41000000 ifs-h3-orangepi.bin
=> go 0x41000000
@endoutput
@group boot_kpda
В результате выполнения приведенных выше команд должен запуститься образ ЗОСРВ, выведены сообщения о ходе загрузки и запущен командный интерпретатор. Пример вывода:
@output{shell}
System page at phys:40022000 user:fc410000 kern:fc410000
Starting next program at vfe0820ac
cpu_startnext: cpu0 -> fe0820ac
cpu_startnext: invoking vstart:4100a720 sysp:fc410000 eip:fe0820ac cpu:00000000
VFPv3: fpsid=41023075
coproc_attach(10): attach fe099c78 (fe09b750)
coproc_attach(11): attach fe099c78 (fe09b750)
Welcome to KPDA Neutrino on the OrangePi PC Allwinner H3 (ARMv7 Cortex-A7 QuadCore) - Board
Starting common servers...
Starting UART serial driver...
Starting Network driver...
#
@endoutput
@group boot_auto
Для сохранения параметров загрузки и выполнения требуемого вариант загрузки по-умолчанию автоматически при включении питании модуля, в консоли U-Boot установите переменную окружения @b bootcmd и сохраните значение переменных c помощью команды @b saveenv, например:
@output{shell}
=> setenv kpdaboot_net “tftpboot 0x41000000 ifs-h3-orangepi.bin; go 0x41000000”
=> setenv bootcmd run kpdaboot_net
=> saveenv
@endoutput
@prev{./00-UserGuide.html|table_of_articles||5}

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@page "10-Components" Описание компонентов
@brief Описание компонентов, используемых в ППМ
@@item Список компонентов, входящих в состав ППМ
@@item Список стандартных компонентов, используемых в ППМ
@group table_of_drivers
Описание компонентов, входящих в состав ППМ.
@@table[width:40:60:width] Раздел @| Описание
@group table_of_std_drivers
Описание стандартных компонентов, не входящих в состав ППМ.
@table[width:40:60:width]
@tr Компонент @| Описание
@tr @center @l{devc-ser8250} @endcenter @| Менеджер последовательных 8250-совместимых каналов связи
@endtable
@hint
Опции запуска по умолчанию для указанных компонентов можно посмотреть на странице @link{./Verification.html#base_comp}"Проверка функционирования"@endlink.
@endhint
@prev{./00-UserGuide.html|table_of_articles||10}

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@page "Verification" Проверка функционирования
@brief Проверка функционирования ППМ OrangePi-PC Allwinner-H3 под ЗОСРВ «Нейтрино».
@br
Список проверок:
@@item Базовые проверки функционирования ОС
@@@item Проверка запуска на ПМ ядра ЗОСРВ в составе загружаемого образа
@@@item Проверка запуска компонентов
@@@item Проверка функционирования контроллера DDR памяти
@@@item Проверка функционирования контроллера прерываний
@@@item Проверка функционирования таймера
@@@item Проверка работы ЗОСРВ на ЦП в режиме симметричной мультипроцессорности (SMP) с поддержкой всех CPU ядер типа Cortex-A7
@@item Проверки интерфейсов
@@@item Проверка драйвера контроллера UART
@@@item Проверка драйвера контроллера Gigabit Ethernet
@par Тестовый стенд
Тестовый стенд представляет из себя отладочный модуль OrangePi-PC, соединённый с инструментальным ПК по интерфейсам RS-232 и Ethernet.
@br
На инструментальный ПК должно быть установлено:
@ul
@item ОС семейства GNU Linux, например, Ubuntu 20.04
@item Комплект разработчика для ЗОСРВ «Нейтрино»
@item ППМ OrangePi-PC Allwinner-H3
@item Терминальная программа для отладочной консоли модуля OrangePi-PC, например, minicom
@endul
@par Подготовка
Перед проведением проверок необходимо запустить ЗОСРВ «Нейтрино» на отладочном модуле OrangePi-PC в соответствии с главой документации @link{./Boot.html}Загрузка образа ОС@endlink.
@br
Дополнительные тестовые программы @a rr, @a ticksize и другие не входят в состав ППМ и должны быть самостоятельно загружены из @link{https://git.kpda.ru/utils/hw}публичного git-репозитория@endlink и собраны командой:
@output{shell}
$ cd utils
$ make install
@endoutput
Затем следует скопировать @a armle-v7 версии тестовых программ на SD карту памяти и подключить её к OrangePi-PC или передать файлы по сети с помощью @l{Настройка FTP сервера|FTP} или @l{Настройка NFS сервера|NFS}.
@group base
@group base_run
В последовательном терминале выполнить команду:
@output{shell}# uname -s @endoutput
Проверка считается выполненной успешно, если в терминале будет выведено сообщение вида:
@output{shell}KPDA @endoutput
@group base_comp
Для вывода информации о запущенных компонентов выполнить команду @l{pidin|pidin ar}:
@output{shell}
# pidin ar
pid Arguments
1 procnto-smp -vvv -ae
2 slogger -s 16384k
3 pipe
4 devc-ser8250 -e -F -b115200 -c24000000/16 0x01C28000^2,32
5 random -t
6 io-pkt-v4-hc-ksz -dsun8i
4103 sh
4104 pidin ar
@endoutput
@group base_mem
Для вывода информации о процессоре и доступной оперативной памяти выполнить команду @l{pidin|pidin info}:
@output{shell}
# pidin info
CPU:ARM Release:trunk FreeMem:992Mb/1024Mb BootTime:Jan 01 00:00:00 UTC 1970
Processes: 8, Threads: 28
Processor1: 1091551349 Cortex A7 228MHz FPU
Processor2: 1091551349 Cortex A7 228MHz FPU
Processor3: 1091551349 Cortex A7 228MHz FPU
Processor4: 1091551349 Cortex A7 228MHz FPU
@endoutput
Для проверки функционирования контроллера оперативной памяти используется утилита @a memcheck. Ее требуется запустить и дождаться завершения проверки:
@output{shell}# /tmp/memcheck @endoutput
Проверка считается выполненной успешно, если выведено сообщение:
@output{shell}PASS: all memory allocated @endoutput
@group base_interrupts
Для вывода информации о используемых прерываниях выполнить команду @l{pidin|pidin ir}:
@output{shell}
# pidin ir
pid tid name
1 1 procnto-smp
1 2 procnto-smp
1 3 procnto-smp
1 4 procnto-smp
0 0x1b 0 -P- @0xfe08a2c4:0x0
1 5 procnto-smp
1 6 procnto-smp
1 7 procnto-smp
1 8 procnto-smp
1 9 procnto-smp
1 10 procnto-smp
1 11 procnto-smp
1 12 procnto-smp
1 13 procnto-smp
1 14 procnto-smp
1 16 procnto-smp
2 1 slogger
3 1 pipe
3 2 pipe
3 3 pipe
4 1 devc-ser8250
1 0x20 0 --- @0x804ab30:0x805d1c0
5 1 random
5 2 random
5 3 random
6 1 io-pkt-v4-hc-ksz
6 2 io-pkt-v4-hc-ksz
2 0x72 0 T-- @0x78002d5c:0x818f2c0
6 3 io-pkt-v4-hc-ksz
4103 1 sh
20488 1 pidin
@endoutput
Проверка считается пройденной успешно, если вывод утилиты @l{pidin|pidin ir} содержит информацию об обработчиках прерывания, принадлежащих выполняемым процессам, в формате
@output{shell}
pid tid Имя процесса
id прерывания vector mask_count flags handler:area
@endoutput
@group base_system_timer
Для проверки функционирования системного таймера необходимо воспользоваться программой @a ticksize:
@output{shell}# /tmp/ticksize @endoutput
Проверка считается выполненной успешно, если вывод данной программы содержит аналогичные строки:
@output{shell}
System timer ticksize: 1000 mks
Measuring system timer interrupt latency for 10 sec...
------------------------------------
System Timer Latency = 0.54 mks
------------------------------------
@endoutput
@group base_smp
Для вывода информации о количестве процессоров выполнить команду @l{pidin|pidin info}:
@output{shell}
# pidin info
CPU:ARM Release:trunk FreeMem:992Mb/1024Mb BootTime:Jan 01 00:00:00 UTC 1970
Processes: 8, Threads: 28
Processor1: 1091551349 Cortex A7 228MHz FPU
Processor2: 1091551349 Cortex A7 228MHz FPU
Processor3: 1091551349 Cortex A7 228MHz FPU
Processor4: 1091551349 Cortex A7 228MHz FPU
@endoutput
Для проверки функционирования на всех ядрах выполнить следующее:
@output{shell}
# for cpu in 0 1 2 3; do on -C$cpu pidin -P pidin -fl; done
@endoutput
Проверка считается выполненной успешно, если вывод содержит следующие строки:
@output{shell}
cpu
0
cpu
1
cpu
2
cpu
3
@endoutput
@group bsp
@group bsp_uart
Для работы с последовательным портом используется драйвер @l{devc-ser8250}. Настройки последовательного порта по умолчанию: скорость 115200, 8 бит, без контроля четности, 1 стоп-бит. В составе загрузочного образа драйвер запускается автоматически.
В случае успешного запуска драйвера в директории `/dev/` будет создано устройство @c ser1.
@output{shell}
# ls /dev/ser*
/dev/ser1
@endoutput
Для проверки функционирования драйвера UART подключить ПМ к ПК через преобразователь по USB в один из разъемов и запустить терминальную программу @a minicom. В последовательном или удалённом терминале выполнить следующую команду:
@output{shell}
# echo Test message > /dev/ser1
@endoutput
Проверка считается выполненной успешно, если в терминальной программе будет выведено сообщение:
@output{shell}
Test message
@endoutput
@group bsp_ethernet
Для работы с контроллером интерфейса Gigabit Ethernet используется драйвер @l{devnp-sun8i.so} и менеджер ресурсов @l{io-pkt-*|io-pkt-v4-hc-ksz}. В составе загрузочного образа драйвер запускается автоматически. Для вывода информации о сетевых интерфейсах выполнить команду @l{ifconfig}.
В случае успешного запуска драйвера будет создан сетевой интерфейс @a xzynq0 и в результате выполнения команды @l{ifconfig} на экран будут выведены данные, аналогичные следующим, с указанием текущего ip-адреса, маски и широковещательного адреса:
@output{shell}
lo0: flags=8049<UP,LOOPBACK,RUNNING,MULTICAST> mtu 33192
inet 127.0.0.1 netmask 0xff000000
sun0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> mtu 1500
address: f2:b4:15:84:4c:8b
media: Ethernet autoselect (100baseTX full-duplex)
status: active
inet <ip адрес> netmask <маска> broadcast <широковещательный адрес>
@endoutput
Для проверки функционирования сетевого обмена выполнить следующую команду, инициирующую отправку ICMP пакетов существующему сетевому узлу:
@output{shell}
# ping -c 3 <ip получателя>
PING <ip получателя> (<ip получателя>): 56 data bytes
64 bytes from <ip получателя>: icmp_seq=0 ttl=64 time=0 ms
64 bytes from <ip получателя>: icmp_seq=1 ttl=64 time=0 ms
64 bytes from <ip получателя>: icmp_seq=2 ttl=64 time=0 ms
----<ip получателя> PING Statistics----
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0/0/0 ms variance = 0 ms^2
@endoutput
Проверка считается выполненной успешно, если все 3 пакета были успешно получены (процент потерь равен нулю).
@prev{./00-UserGuide.html|table_of_articles||11}

8
docs/20-KnownIssues.dox Обычный файл
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@page "KnownIssues" Известные особенности
@brief Известные особенности и ограничения текущей версии пакета поддержки
@br
Известные особенности отсутствуют
@prev{./00-UserGuide.html|table_of_articles||20}

5
docs/21-ReleaseNotes.dox Обычный файл
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@page "ReleaseNotes" Журнал изменений BSP для OrangePi-PC Allwinner-H3
@brief Журнал и история изменений компонентов пакета поддержки
@prev{./00-UserGuide.html|table_of_articles||21}

11
docs/caption.inc Обычный файл
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#!/bin/sh
################################################################
## Переменные окружения с названием документа для gendoc
################################################################
export GENDOC_PROJECT_NAME="Руководство пользователя"
export GENDOC_PROJECT_BRIEF="Руководство пользователя пакета поддержки платы OrangePi-PC на основе интегральной микросхемы Allwinner-H3 под ЗОСРВ «Нейтрино»"
export GENDOC_PROJECT_VERSION=""
export GENDOC_IGNORE_MISSING_AUTOLINK_ERRORS="yes"

18
exclude.inc Обычный файл
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# Include file for bsp-release.sh script
# Multithread build
JLEVEL=$(nproc)
PACKAGE_SRCZIP_IGNORE=\
"-x*.git/* "\
"-x*.git* "\
"-x*prebuilt/.* "\
"-x*src/hardware/devu/* "\
""
PACKAGE_SRCTAR_IGNORE=\
"--exclude=src/hardware/devu"\
""
PACKAGE_BINTAR_IGNORE=\
""

19
images/Makefile Обычный файл
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ROOT_DIR := $(notdir $(CURDIR))
ifndef QCONFIG
QCONFIG=qconfig.mk
endif
include $(QCONFIG)
HOST_MKIFS := mkifs
SUFFIXES := .build .ifs .raw
.PHONY: all clean
all: ifs-h3-orangepi.bin
clean:
$(RM_HOST) ifs-h3-orangepi.bin
ifs-h3-orangepi.bin: orangepi.build
$(HOST_MKIFS) -r../install -v $(MKIFSFLAGS) $^ $@

216
images/orangepi.build Обычный файл
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###########################################################################
##
## KPDA Neutrino trunk on the OrangePi PC Allwinner H3 (ARMv7 Cortex-A7 QuadCore) Board
##
###########################################################################
##
## SUPPORTED DEVICES:
##
## UART_SERIAL: devc-ser8250
## NETWORK: devnp-sun8i
##
###########################################################################
##
## NOTES:
##
###########################################################################
###########################################################################
## START OF BUILD SCRIPT
###########################################################################
[image=0x41000000]
[virtual=armle-v7,raw] .bootstrap = {
startup-orangepi -vvv
PATH=:/proc/boot:/bin:/usr/bin:/sbin:/usr/sbin LD_LIBRARY_PATH=:/proc/boot:/lib:/usr/lib:/lib/dll procnto-smp -vvv -ae
}
[+script] .script = {
# Initialise the console
procmgr_symlink ../../proc/boot/libc.so.3 /usr/lib/ldqnx.so.2
display_msg Welcome to KPDA Neutrino on the OrangePi PC Allwinner H3 (ARMv7 Cortex-A7 QuadCore) - Board
display_msg Starting common servers...
slogger -s 16384k
pipe
#######################################################################
## UART driver
## UART0 (0x01C28000) -> stdout
#######################################################################
display_msg Starting UART serial driver...
devc-ser8250 -e -F -b115200 -c24000000/16 0x01C28000^2,32
waitfor /dev/ser1
reopen /dev/ser1
#######################################################################
## These env variables are inherited by all the programs which follow
#######################################################################
SYSNAME=nto
TERM=qansi
HOME=/
PATH=:/proc/boot:/bin:/usr/bin:/sbin:/usr/sbin:/opt/bin:/usr/photon/bin
LD_LIBRARY_PATH=:/proc/boot:/lib:/usr/lib:/lib/dll:/opt/lib
random -t
#######################################################################
## Network driver
#######################################################################
display_msg Starting Network driver...
io-pkt-v4-hc-ksz -dsun8i
ifconfig sun0 192.168.1.2/24 up
[+session] sh &
}
# Redirect console messages
[type=link] /bin/sh=/proc/boot/ksh
[type=link] /dev/console=/dev/ser1
[type=link] /tmp=/dev/shmem
[type=link] /var/log=/tmp
[type=link] /usr/tmp=/tmp
[type=link] /bin/login=/proc/boot/login
###########################################################################
## Системные библиотеки
###########################################################################
libc.so
libm.so
libz.so
libc.so.3
[type=link] /lib/libc.so=/proc/boot/libc.so.3
[type=link] /lib/libc.so.2=/proc/boot/libc.so.3
[type=link] /lib/libc.so.3=/proc/boot/libc.so.3
[type=link] /usr/lib/ldqnx.so.2=/proc/boot/libc.so.3
###########################################################################
## Библиотеки работы с диском и файловые системы
###########################################################################
fs-qnx4.so
fs-qnx6.so
libcam.so
io-blk.so
cam-disk.so
fs-dos.so
cam-cdrom.so
fs-cd.so
fs-udf.so
###########################################################################
## Драйверы USB и устройств ввода
###########################################################################
libhiddi.so
libusbdi.so
devu-ehci.so
devu-ohci.so
devh-usb.so
###########################################################################
## Сетевые драйверы
###########################################################################
devnp-shim.so
libsocket.so
lsm-qnet.so
devnp-sun8i.so
[data=c]
#######################################################################
## Драйверы последовательных портов
#######################################################################
devc-ser8250
/bin/stty=stty
#######################################################################
## Драйверы ввода
#######################################################################
devu-kbd
devu-mouse
###########################################################################
## Системные сервисы и утилиты
###########################################################################
ksh
sh
pipe
mqueue
cp
mkdir
ls
pidin
rm
mv
on
uname
slay
sync
mount
umount
shutdown
less
setconf
getconf
grep
rtc
date
fdisk
cat
chown
chmod
use
which
dcheck
usb
pci
devc-pty
waitfor
sloginfo
sleep
date
###########################################################################
## Менеджеры ресурсов: PCI, сеть, графика, аудио, драйвер диска и т.д.
###########################################################################
io-pkt-v4-hc-ksz
io-usb
io-hid
usb
devb-umass
slogger
###########################################################################
## Сетевые утилиты
###########################################################################
fs-nfs3
hostname
ifconfig
inetd
ping
telnetd
ftpd
nicinfo
dhcp.client
if_up
netstat
route
random
###########################################################################
## END OF BUILD SCRIPT
###########################################################################

15
images/tftp.sh Исполняемый файл
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#!/bin/bash
set -ex
TFTP_SERIAL=${TTY_SERIAL:-/dev/ttyUSB0}
TFTP_CLIENT=172.16.7.99
TFTP_SERVER=172.16.7.7
image="ifs-h3-orangepi.bin"
tftp -R 6969:6969 $TFTP_SERVER -c put $image $image
echo "setenv ipaddr $TFTP_CLIENT" > $TFTP_SERIAL
echo "setenv serverip $TFTP_SERVER" > $TFTP_SERIAL
echo "setenv gatewayip $TFTP_SERVER" > $TFTP_SERIAL
echo "tftpboot 0x41000000 $image; go 0x41000000" > $TFTP_SERIAL

4
src/Makefile Обычный файл
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LIST=ALL
EARLY_DIRS=lib
LATE_DIRS=apps
include recurse.mk

3
src/hardware/Makefile Обычный файл
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LIST=hardware
EARLY_DIRS=dma devu
include recurse.mk

2
src/hardware/devnp/Makefile Обычный файл
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LIST=DEVNP
include recurse.mk

2
src/hardware/devnp/sun8i/Makefile Обычный файл
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LIST=CPU
include recurse.mk

8
src/hardware/devnp/sun8i/arm/Makefile Обычный файл
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LIST=VARIANT
ifndef QRECURSE
QRECURSE=recurse.mk
ifdef QCONFIG
QRDIR=$(dir $(QCONFIG))
endif
endif
include $(QRDIR)$(QRECURSE)

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include ../../common.mk

25
src/hardware/devnp/sun8i/common.mk Обычный файл
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#
# (c) 2014-2019, SWD Embedded Systems Limited, http://www.kpda.ru
#
ifndef QCONFIG
QCONFIG=qconfig.mk
endif
include $(QCONFIG)
ISKERNEL := 1
NETDRIVERS_MK = $(firstword $(wildcard $(MKFILES_ROOT)/netdrivers.mk ../../../../../netdrivers.mk ../../netdrivers.mk))
include $(NETDRIVERS_MK)
LIBS = drvrS cacheS
LIBS += $(foreach libpath,$(LIBVPATH), $(if $(wildcard $(libpath)/libnetdrvrS.a), netdrvrS) )
NAME = devnp-sun8i
CCFLAGS += -Wall -Wextra -pedantic -Werror -std=gnu99
define PINFO
PINFO DESCRIPTION=sample io-pkt ethernet driver.
endef
include $(MKFILES_ROOT)/qtargets.mk

41
src/hardware/devnp/sun8i/devnp-sun8iso.dox Обычный файл
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@page "devnp-sun8iso" devnp-sun8i.so
@brief Драйвер Ethernet контроллеров семейства процессоров Allwinner sun8i (на базе Cortex-A7)
@remark io-pkt-* -d sun8i [опция[,опция ...]] ...
@caution
Для разделения опций используется запятая (но не пробелы).
@endcaution
@par Платформы:
ЗОСРВ «Нейтрино»
@arch{armv7}
@par Описание:
Драйвер @a devnp-sun8i.so управляет Ethernet контроллерами семейства процессоров Allwinner sun8i (на базе Cortex-A7). Это драйвер @l{io-pkt-*}; имена интерфейсов назначаются в виде @a sunX, где @a X – целое число.
@par Поддерживаемые устройства:
@ul
@item Ethernet контроллер процессора Allwinner H3
@endul
@par Примеры:
Запуск @l{io-pkt-*} с использованием драйвера @a devnp-sun8i.so и полного стека TCP/IP:
@output{shell}io-pkt -d sun8i
ifconfig sun0 192.168.0.10 @endoutput
@par Классификация:
Базовые подсистемы ЗОСРВ «Нейтрино», Драйверы
@par Тематические ссылки:
@l{Драйверы|devn-*}, @l{Драйверы|devnp-*}, @l{ifconfig}, @l{io-pkt-*}, @l{nicinfo}
@prev{./10-Components.html|table_of_drivers||50}

36
src/hardware/devnp/sun8i/netdrivers.mk Обычный файл
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# We link the stack with -E so a lot of the undefined
# references get resolved from the stack itself. If
# you want them listed at link time, turn off
# --allow-shlib-undefined and replace with --warn-once
# if desired.
#LDFLAGS+=-Wl,--warn-once
LDFLAGS+=-Wl,--allow-shlib-undefined
NETDRVR_ROOT:=$(patsubst %/,%, $(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
DEVNP_ROOT:=$(NETDRVR_ROOT)/hardware/devnp
BSDDRVR_ROOT:=$(DEVNP_ROOT)/bsd
LIBNBDRVR_ROOT:=$(NETDRVR_ROOT)/lib/libnbdrvr
HDR_PATH=$(INSTALL_ROOT_HDR)/io-pkt
PUBLIC_HDR_PATH=$(KPDA_TARGET)/usr/include/io-pkt
# Check for staging area first
EXTRA_INCVPATH+= $(HDR_PATH) $(HDR_PATH)/sys-nto
# Use headers installed in system if staging area not available
EXTRA_INCVPATH+= $(PRODUCT_ROOT) $(PUBLIC_HDR_PATH) $(PUBLIC_HDR_PATH)/sys-nto
ifneq ($(NEED_QNXH),)
CCFLAGS += -Wp,-include -Wp,$(if $(wildcard $(HDR_PATH)),$(HDR_PATH)/qnx.h,$(PUBLIC_HDR_PATH)/qnx.h)
endif
ifneq ($(NEED_LIBNBDRVR),)
EXTRA_INCVPATH+=$(LIBNBDRVR_ROOT)
endif
ifneq ($(ISKERNEL),)
CCFLAGS += -D_KERNEL
endif
CCFLAGS_e2k += -fkernel
CCFLAGS += $(CCFLAGS_$(CPU))
# gcc sometime after 2.95.3 added a builtin log()
CCFLAGS += -fno-builtin-log

1497
src/hardware/devnp/sun8i/sun8i.c Обычный файл

Разница между файлами не показана из-за своего большого размера Загрузить разницу

276
src/hardware/devnp/sun8i/sun8i.h Обычный файл
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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
#ifndef __SUN8I_H__
#define __SUN8I_H__
#define BIT(bit) (UINT32_C(1) << bit)
#define GENMASK32(a, b) ((UINT32_MAX >> (32 - (b) - 1)) & (UINT32_MAX << (a)))
// Syscon address space
#define AW_H3_SYS_CTRL_BASE 0x01c00000
#define AW_H3_SYS_CTRL_SIZE 0x1000
// EMAC Clock Register, Syscon
#define EMAC_CLK_REG 0x0030
#define H3_EPHY_DEFAULT_VALUE 0x58000
#define H3_EPHY_DEFAULT_MASK GENMASK32(16, 31)
#define H3_EPHY_ADDR_SHIFT 20
#define REG_PHY_ADDR_MASK GENMASK32(0, 4)
#define SC_EPIT BIT(2) // 1: RGMII, 0: MII
#define SC_RMII_EN BIT(13)
#define H3_EPHY_SELECT BIT(15) // 1: internal PHY, 0: external PHY
#define H3_EPHY_SHUTDOWN BIT(16) // 1: shutdown, 0: power up
#define H3_EPHY_LED_POL BIT(17) // 1: active low, 0: active high
#define H3_EPHY_CLK_SEL BIT(18) // 1: 24MHz, 0: 25MHz
#define SC_ETCS_MASK 0x3
// CCU address space
#define AW_H3_CCU_BASE 0x01c20000
#define AW_H3_CCU_SIZE 0x400
// Clock source register, CCU
#define BUS_CLK_GATING_REG0 0x0060
#define BUS_CLK_GATING_REG0_EMAC_GATING BIT(17)
// Reset source register, CCU
#define BUS_SOFT_RST_REG0 0x02C0
#define BUS_SOFT_RST_REG0_EMAC_RST BIT(17)
// EPHY clock, CCU
#define BUS_CLK_GATING_REG4 0x0070
#define BUS_CLK_GATING_REG4_EPHY_GATING BIT(0)
// EPHY reset, CCU
#define BUS_SOFT_RST_REG2 0x02c8
#define BUS_SOFT_RST_REG2_EPHY_RST BIT(2)
// EMAC address space
#define SUN8I_EMAC_BASE 0x01c30000
#define SUN8I_EMAC_SIZE 0x10000
// EMAC Basic Control 0 Register (Link control)
#define EMAC_CTL0 0x0000
#define EMAC_CTL0_FULL_DUPLEX BIT(0)
#define EMAC_CTL0_LOOPBACK BIT(1)
#define EMAC_CTL0_SPEED_MASK (BIT(3) | BIT(2))
#define EMAC_CTL0_10 (BIT(3))
#define EMAC_CTL0_100 (BIT(3) | BIT(2))
// EMAC Basic Control 1 Register
#define EMAC_CTL1 0x0004
#define EMAC_CTL1_SOFT_RST BIT(0) // Soft reset
#define EMAC_CTL1_BURST_SIZE(val) ((val & 0x3f) << 24) // RX/TX DMA transfer burst len
// EMAC Interrupt Status/Enable Register
#define EMAC_INT_STA 0x0008
#define EMAC_INT_EN 0x000c
#define EMAC_INT_RX_INT BIT(8) // RX interrupt
#define EMAC_INT_TX_INT BIT(0) // TX interrupt
#define EMAC_INT_TX_UNDERFLOW_INT_EN BIT(4) // TX FIFO underflow error
#define EMAC_INT_RX_UNDERFLOW_INT_EN BIT(12) // RX FIFO underflow error
#define EMAC_INT_EN_MASK (EMAC_INT_RX_INT | EMAC_INT_TX_INT | EMAC_INT_RX_UNDERFLOW_INT_EN | EMAC_INT_TX_UNDERFLOW_INT_EN)
// EMAC Transmit Control 0 Register
#define EMAC_TX_CTL0 0x0010
#define EMAC_TX_CTL0_TX_EN BIT(31) // Enable transmitter
// EMAC Transmit Control 1 Register
#define EMAC_TX_CTL1 0x0014
#define EMAC_TX_CTL1_TX_MD BIT(1) // Transmission starts after a full frame located in TX DMA FIFO
#define EMAC_TX_CTL1_TX_DMA_EN BIT(30) // Start and run TX DMA
#define EMAC_TX_CTL1_TX_DMA_START BIT(31) // Start and run TX DMA
// EMAC Transmit DMA Descriptor List Address Register
#define EMAC_TX_DMA_DESC 0x0020
// EMAC Receive Control 0 Register
#define EMAC_RX_CTL0 0x0024
#define EMAC_RX_CTL0_RX_EN BIT(31) // Enable receiver
// EMAC Receive Control 1 Register
#define EMAC_RX_CTL1 0x0028
#define EMAC_RX_CTL1_RX_MD BIT(1) // RX DMA reads data from RX DMA FIFO to host memory after a complete frame has been written to RX DMA FIFO
#define EMAC_RX_CTL1_RX_DMA_EN BIT(30) // Start and run RX DMA
// EMAC Receive DMA Descriptor List Address Register
#define EMAC_RX_DMA_DESC 0x0034
// EMAC MAC Address 0 High Register
#define EMAC_ADDR0_HIGH 0x0050
// EMAC MAC Address 0 Low Register
#define EMAC_ADDR0_LOW 0x0054
// EMAC MII Command Register
#define EMAC_MII_CMD 0x0048
#define MDIO_CMD_MII_BUSY BIT(0)
#define MDIO_CMD_MII_WRITE BIT(1)
#define MDIO_CMD_MII_PHY_REG_ADDR_MASK GENMASK32(4, 8)
#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
#define MDIO_CMD_MII_PHY_ADDR_MASK GENMASK32(12, 16)
#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
#define MDIO_CMD_MDC_DIV_RATIO_M_128 (BIT(20) | BIT(21))
// EMAC MII Data Register
#define EMAC_MII_DATA 0x004c
// Descriptors macros
#define CONFIG_ETH_BUFSIZE 2048 // Note must be dma aligned
#define CONFIG_ETH_RXSIZE 2044 // Note must fit in ETH_BUFSIZE
#define SUN8I_DESC(buf, idx) (&((sun8i_desc_t *)(buf)->area)[(idx)])
// TX descriptors
#define CONFIG_TX_DESCR_NUM 32
#define SUN8I_TX_DESC(sun8i, idx) SUN8I_DESC(&(sun8i)->txb, (idx))
#define TX_DESC_CTL BIT(31)
#define TX_INT_CTL BIT(31)
#define LAST_DESC BIT(30)
#define FIR_DESC BIT(29)
#define TX_HEADER_ERR BIT(16)
#define TX_LENGHT_ERR BIT(14)
#define TX_PAYLOAD_ERR BIT(12)
#define TX_CRS_ERR BIT(10)
#define TX_COL_ERR_0 BIT(9)
#define TX_COL_ERR_1 BIT(8)
#define TX_COL_CNT_MASK GENMASK32(3, 6)
#define TX_COL_CNT_SHIFT 3
#define TX_COL_CNT(status) (((status) & TX_COL_CNT_MASK) >> TX_COL_CNT_SHIFT)
#define TX_DEFER_ERR BIT(2)
#define TX_UNDERFLOW_ERR BIT(1)
#define TX_DEFER BIT(0)
#define ERROR_STATUS_MASK (TX_HEADER_ERR | TX_LENGHT_ERR | TX_PAYLOAD_ERR | TX_CRS_ERR | TX_COL_ERR_0 | TX_DEFER_ERR | TX_UNDERFLOW_ERR)
// RX descriptors
#define CONFIG_RX_DESCR_NUM 32
#define SUN8I_RX_DESC(sun8i, idx) SUN8I_DESC(&(sun8i)->rxb, (idx))
#define RX_DESC_CTL BIT(31)
#define RX_LAST_DESC BIT(8)
#define RX_DESC_FRM_SIZE_MASK GENMASK32(16, 29)
#define RX_DESC_FRM_SIZE(status) (((status) & RX_DESC_FRM_SIZE_MASK) >> 16)
#define CONFIG_SYS_HZ 1000
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
#define EMAC_SOFT_RESET_TIMEOUT_USEC (100 * 1000)
#define SPI_INTERRUPT_START 0x20
#define SUN8I_H3_INTERRUPT (SPI_INTERRUPT_START + 0x52)
const uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
enum emac_variant
{
H3_EMAC = 2,
};
enum
{
PHY_INTERFACE_MODE_MII = 1,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
};
struct sun8i_desc
{
uint32_t status;
uint32_t size;
uint32_t addr;
uint32_t next;
} __attribute__ ((packed));
typedef struct sun8i_desc sun8i_desc_t;
struct desc_buffer
{
void *area;
size_t size;
off_t dma;
int prot_flags;
int map_flags;
int tmem_fd;
struct mbuf **mbufs_set;
int head;
int tail;
int cnt;
int free_cnt;
struct
{
uint64_t header;
uint64_t length;
uint64_t payload;
uint64_t crs;
uint64_t coll0;
uint64_t coll1;
uint64_t coll_cnt;
uint64_t defer;
uint64_t underflow;
} err;
};
typedef struct desc_buffer desc_buffer_t;
struct sun8i_dev
{
struct device dev;
struct ethercom ec;
struct ieee80211com ic;
struct mii_data bsd_mii;
int iid;
int intr_cnt;
int intr_spurious;
void *sd_hook;
uintptr_t syscon_base;
uintptr_t clk_base;
uintptr_t emac_base;
enum emac_variant variant;
int use_internal_phy;
uint32_t mii_mode;
uint32_t adv;
nic_config_t cfg;
nic_stats_t stats;
struct _iopkt_self *iopkt;
struct _iopkt_inter inter;
int speed;
int duplex;
desc_buffer_t txb;
desc_buffer_t rxb;
struct cache_ctrl cachectl;
uint32_t irq_src;
mdi_t *mdi;
struct callout mii_callout;
int linkup;
int start_running;
};
typedef struct sun8i_dev sun8i_dev_t;
struct sun8i_attach_args
{
uintptr_t syscon_base;
uintptr_t clk_base;
uintptr_t emac_base;
enum emac_variant variant;
int use_internal_phy;
int phy_addr;
uint32_t mii_mode;
nic_config_t cfg;
struct _iopkt_self *iopkt;
char *options;
};
#endif

4
src/hardware/startup/Makefile Обычный файл
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LATE_DIRS=boards
CPULIST=arm
VARIANTLIST=v7
include recurse.mk

2
src/hardware/startup/boards/Makefile Обычный файл
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LIST=BOARD
include recurse.mk

128
src/hardware/startup/boards/common.mk Обычный файл
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#
# (c) 2010-2019, SWD Embedded Systems Limited, http://www.kpda.ru
#
ifndef QCONFIG
QCONFIG=qconfig.mk
endif
include $(QCONFIG)
PSTAG_64 = .64
LIB_VARIANT = $(subst .o,,a.$(COMPOUND_VARIANT))$(PSTAG_$(PADDR_SIZE))
LINKER_TYPE=BOOTSTRAP
INSTALLDIR = boot/sys
LIBS = startup$(subst .,-,$(PSTAG_$(PADDR_SIZE)))
LIBS += $(foreach lib,ucl lz4-dec zstd-dec,$(if $(wildcard $(addsuffix /lib$(lib).a,$(LIBVPATH))), $(lib)) )
LIBS += drvr
# The board level is one up from the CPU level
BOARD_ROOT=$(patsubst %/,%,$(dir $(CPU_ROOT)))
BOARD=$(notdir $(BOARD_ROOT))
NAME = startup-$(BOARD)
EXTRA_SILENT_VARIANTS+=$(subst -, ,$(BOARD) $(SECTION))
USEFILE =
EXTRA_SRCVPATH += $(BOARD_ROOT)/overrides
EXTRA_INCVPATH += $(BOARD_ROOT)/overrides \
$(LIBSTARTUP_ROOT)/$(CPU)/$(LIB_VARIANT) \
$(LIBSTARTUP_ROOT)/$(CPU) \
$(LIBSTARTUP_ROOT) \
$(LIBSTARTUP_ROOT)/public
EXTRA_LIBVPATH += $(LIBSTARTUP_ROOT)/$(CPU)/$(LIB_VARIANT) \
$(USE_ROOT_LIB) \
$(QNX_TARGET)/$(CPUVARDIR)/lib \
$(QNX_TARGET)/$(CPUVARDIR)/usr/lib
#LDBOOTSTRAPPOST_nto_x86_gcc_qcc:=$(subst -lc, -L$(QNX_TARGET)/x86/lib -lc, $(LDBOOTSTRAPPOST_nto_x86_gcc_qcc))
CCFLAG_64 = -D_PADDR_BITS=64
CCFLAGS_gcc_ = -O2 -fomit-frame-pointer
CCFLAGS_gcc_qcc = -O2 -Wc,-fomit-frame-pointer
CCFLAGS_$(BUILDENV) = -DBUILDENV_$(BUILDENV)
CCFLAGS = $(CCFLAGS_$(COMPILER_TYPE)_$(COMPILER_DRIVER)) $(CCFLAG_$(PADDR_SIZE)) $(CCFLAGS_$(BUILDENV))
CCFLAGS += -DBOARDNAME=\"$(BOARD)\"
LDFLAGS_gcc_qcc = -M
LDFLAGS = $(LDFLAGS_$(COMPILER_TYPE)_$(COMPILER_DRIVER))
EXTRA_ICLEAN=$(BOARD_ROOT)/*.pinfo
FILE_INFO = 0 0 644
define POST_INSTALL
-$(foreach build,$(EXAMPLE_BUILDFILES), \
$(CP_HOST) $(build) $(INSTALL_ROOT_nto)/$(CPUVARDIR)/boot/build/$(BOARD)-$(notdir $(build));)
-$(foreach build,$(MAIN_BUILDFILES) $(EXAMPLE_READMES), \
$(CP_HOST) $(build) $(INSTALL_ROOT_nto)/$(CPUVARDIR)/boot/build/$(BOARD).$(notdir $(build));)
endef
include $(MKFILES_ROOT)/qmacros.mk
ADD_USAGE=
-include $(PROJECT_ROOT)/roots.mk
ifndef LIBSTARTUP_ROOT
LIBSTARTUP_ROOT=$(PRODUCT_ROOT)/lib
endif
EXAMPLE_BUILDFILES:=$(wildcard *.build $(BOARD_ROOT)/*.build)
MAIN_BUILDFILES:=$(wildcard build $(BOARD_ROOT)/build)
EXAMPLE_READMES:=$(wildcard $(BOARD_ROOT)/*readme)
EBF_PINFOS:=$(addsuffix .pinfo, $(EXAMPLE_BUILDFILES))
ERM_PINFOS:=$(addsuffix .pinfo, $(EXAMPLE_READMES))
EXTRA_DEPS = $(EBF_PINFOS) $(ERM_PINFOS)
include $(BOARD_ROOT)/pinfo.mk
-include $(BOARD_ROOT)/extra.mk
include $(MKFILES_ROOT)/qtargets.mk
-include $(PROJECT_ROOT)/announce.mk
define DO_PINFO
@$(ECHO_HOST) >$@ STATE=Experimental
@$(ECHO_HOST) >>$@ INSTALLDIR=$(CPUVARDIR)/boot/build/
@$(ECHO_HOST) >>$@ INSTALLNAME=$(BOARD).$(patsubst %.pinfo,%,$(@F))
@$(ECHO_HOST) >>$@ NAME=$(patsubst %.pinfo,%,$(@F))
@$(ECHO_HOST) >>$@ USER=$(shell $(USER_HOST))
@$(ECHO_HOST) >>$@ HOST=$(shell $(HOST_HOST))
@$(ECHO_HOST) >>$@ DATE=$(shell $(DATE_HOST))
endef
$(EBF_PINFOS): $(EXAMPLE_BUILDFILES)
$(DO_PINFO)
@$(ECHO_HOST) >>$@ DESCRIPTION=Example build file for $(NAME)
$(ERM_PINFOS): $(EXAMPLE_READMES)
$(DO_PINFO)
@$(ECHO_HOST) >>$@ DESCRIPTION=Readme file for $(BOARD)
#
# This particular little kludge is to stop GCC from using F.P. instructions
# to move 8 byte quantities around.
#
ifeq ($(BUILDENV),qss)
CC_nto_ppc_gcc += -mno-fp-moves
CC_nto_ppc_gcc_qcc += -Wc,-mno-fp-moves
else
CC_nto_ppc_gcc += -msoft-float
CC_nto_ppc_gcc_qcc += -Wc,-msoft-float
endif
# Prevent building with debug for the standard build.
# Temporary until linker has been changed.
CCOPTS:=$(filter-out -g,$(CCOPTS))
ifeq ($(CPU),x86)
kdebug_ldopts=-Wl,--build-id=md5
LDOPTS_nto_qcc:=$(filter-out $(kdebug_ldopts),$(LDOPTS_nto_qcc))
LDOPTS_nto_gcc:=$(filter-out --build-id=md5,$(LDOPTS_nto_gcc))
endif

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LIST=CPU
include recurse.mk

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LIST=VARIANT
ifndef QRECURSE
QRECURSE=recurse.mk
ifdef QCONFIG
QRDIR=$(dir $(QCONFIG))
endif
endif
include $(QRDIR)$(QRECURSE)

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include ../../../common.mk

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Allwiner H3 SpinLock support
*/
#include "startup.h"
#include <arm/aw_h3.h>
void
aw_h3_spinlock_init(void)
{
uint32_t val1 = in32(AW_H3_CCU_BASE + BUS_CLK_GATING_REG1);
out32(AW_H3_CCU_BASE + BUS_CLK_GATING_REG1,
val1 | CCU_BUS_CLK_GATING1_SPINLOCK);
uint32_t val2 = in32(AW_H3_CCU_BASE + BUS_SOFT_RST_REG1);
out32(AW_H3_CCU_BASE + BUS_SOFT_RST_REG1,
val2 | CCU_BUS_SOFT_RESET1_SPINLOCK);
}
uint32_t
aw_h3_spinlock_check(uint32_t lock)
{
return (in32(AW_H3_SPINLOCK_BASE + SPINLOCK_STATUS_REG) & (1U << lock));
}
void
aw_h3_spinlock_lock(uint32_t lock)
{
for (;;) {
if (in32(AW_H3_SPINLOCK_BASE + SPINLOCK_LOCK_REGN((unsigned) lock)) == 0) {
break;
}
}
}
void
aw_h3_spinlock_unlock(uint32_t lock)
{
out32(AW_H3_SPINLOCK_BASE + SPINLOCK_LOCK_REGN((unsigned) lock), 0);
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Allwinner H3 startup source file.
*/
#ifndef AW_H3_STARTUP_H_
#define AW_H3_STARTUP_H_
/* callout prototype */
extern struct callout_rtn reboot_awh3;
void aw_h3_timer_init(void);
void mdelay(uint32_t ms);
void udelay(uint32_t us);
void aw_h3_spinlock_init(void);
uint32_t aw_h3_spinlock_check(uint32_t lock);
void aw_h3_spinlock_lock(uint32_t lock);
void aw_h3_spinlock_unlock(uint32_t lock);
#endif /* AW_H3_STARTUP_H_ */

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Allwinner H3 Timer support
*/
#include "startup.h"
#include <arm/aw_h3.h>
void
aw_h3_timer_init(void)
{
uint32_t val1 = in32(AW_H3_CCU_BASE + AVS_CLK_REG);
out32(AW_H3_CCU_BASE + AVS_CLK_REG, val1 | CCU_THS_CLK_SCLK_GATING);
out32(AW_H3_TIMER_BASE + AVS_CNT_CTL_REG, AVS_CNT1_EN |AVS_CNT0_EN);
out32(AW_H3_TIMER_BASE + AVS_CNT_DIV_REG,
(TIMER_INT_VAL_1MKS << AVS_CNT1_D_SHIFT) | TIMER_INT_VAL_1MS);
out32(AW_H3_TIMER_BASE + AVS_CNT0_REG, 0);
out32(AW_H3_TIMER_BASE + AVS_CNT1_REG, 0);
}
void
mdelay(uint32_t ms)
{
uint32_t t1, t2;
t1 = in32(AW_H3_TIMER_BASE + AVS_CNT0_REG);
t2 = t1 + ms;
do {
t1 = in32(AW_H3_TIMER_BASE + AVS_CNT0_REG);
} while (t2 >= t1);
return;
}
void
udelay(uint32_t us)
{
uint32_t t1, t2;
t1 = in32(AW_H3_TIMER_BASE + AVS_CNT1_REG);
t2 = t1 + us;
do {
t1 = in32(AW_H3_TIMER_BASE + AVS_CNT1_REG);
} while (t2 >= t1);
return;
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* OrangePi PC Allwinner H3 (QuadCore Cortex-A7)
*/
#ifndef __ORANGEPI_H_INCLUDED
#define __ORANGEPI_H_INCLUDED
#include <arm/aw_h3.h>
#define ORANGEPI_PC_RAM_SIZE 1024 // MB
#endif /* __ORANGEPI_H_INCLUDED */

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* SUN8I SMP support
*/
#include "startup.h"
#include <arm/aw_h3.h>
#define BIT(nr) (1UL << (nr))
extern void smp_spin();
unsigned startup_smp_start;
unsigned
board_smp_num_cpu()
{
if (debug_flag) {
kprintf("Initializing SMP for %d CPUs...\n", AW_H3_NUM_OF_CORES);
}
return AW_H3_NUM_OF_CORES;
}
void
board_smp_init(struct smp_entry *smp, unsigned num_cpus)
{
smp->send_ipi = (void *)&sendipi_gic;
}
int
board_smp_start(unsigned cpu, void (*start)(void))
{
uint32_t reg;
startup_smp_start = (uint32_t) start;
if (debug_flag > 1) {
kprintf("board_smp_start: cpu%d -> %x\n", cpu, start);
}
aw_h3_spinlock_lock((uint32_t) cpu);
/* Set CPU boot address */
out32(AW_H3_CPUCFG_BASE + CPUCFG_PRIVATE0_REG, startup_smp_start);
/* Assert the CPU core in reset */
out32(AW_H3_CPUCFG_BASE + CPUCFG_CPU_RST_CTRL_REG(cpu), 0);
/* Assert the L1 cache in reset */
reg = in32(AW_H3_CPUCFG_BASE + CPUCFG_GEN_CTRL_REG);
out32(AW_H3_CPUCFG_BASE + CPUCFG_GEN_CTRL_REG, reg & ~BIT(cpu));
/* Clear CPU power-off gating */
reg = in32(AW_H3_PRCM_BASE + PRCM_CPU_PWROFF_REG);
out32(AW_H3_PRCM_BASE + PRCM_CPU_PWROFF_REG, reg & ~BIT(cpu));
mdelay(1);
/* Deassert the CPU core reset */
out32(AW_H3_CPUCFG_BASE + CPUCFG_CPU_RST_CTRL_REG(cpu), 3);
aw_h3_spinlock_unlock((uint32_t) cpu);
/* Send event to slave CPU to tell them to wake up */
__asm__ __volatile__ ("sev" : : : "memory");
return 1;
}
unsigned
board_smp_adjust_num(unsigned cpu)
{
return cpu;
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Allwinner H3 system reboot
*/
#include "callout.ah"
#include <arm/aw_h3.h>
/*
* -----------------------------------------------------------------------
* Routine to patch callout code
*
* On entry:
* r0 - physical address of syspage
* r1 - virtual address of syspage
* r2 - offset from start of syspage to start of the callout routine
* r3 - offset from start of syspage to read/write data used by callout
* -----------------------------------------------------------------------
*/
patch_reboot:
stmdb sp!,{r4,lr}
add r4, r0, r2 // address of callout routine
/*
* Map Watchdog Timer registers
*/
mov r0, #AW_H3_TIMER_SIZE
ldr r1, Lpaddr
bl callout_io_map
/*
* Patch the callout routine
*/
CALLOUT_PATCH r4, r0, r1, r2, ip
ldmia sp!,{r4,pc}
Lpaddr: .word AW_H3_TIMER_BASE
CALLOUT_START(reboot_awh3, 0, patch_reboot)
/*
* Get the Watchdog Timer base address (patched)
*/
mov ip, #0x000000ff
orr ip, ip, #0x0000ff00
orr ip, ip, #0x00ff0000
orr ip, ip, #0xff000000
/* disable interrupts */
mrs r0, cpsr
orr r0, r0, #0x80
msr cpsr, r0
/* enable WDT */
mov r0, #0x1
str r0, [ip, #WDOG0_CFG_REG]
mov r0, #0x0
str r0, [ip, #WDOG0_MODE_REG]
ldr r0, [ip, #WDOG0_MODE_REG]
orr r0, r0, #0x1
str r0, [ip, #WDOG0_MODE_REG]
0:
b 0b
CALLOUT_END(reboot_awh3)

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* OrangePi PC physical address space information
*/
#include "startup.h"
void
init_asinfo(unsigned mem)
{
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Add Allwinner H3 to the hardware info section of the syspage.
*/
#include "startup.h"
#include "hwinfo_private.h"
#include <drvr/hwinfo.h> // for hwi support routines in libdrvr
#include <arm/aw_h3.h>
void
init_hwinfo()
{
unsigned hwi_bus_internal = 0;
/* add UART */
{
unsigned hwi_off;
hwiattr_uart_t attr = HWIATTR_UART_T_INITIALIZER;
struct hwi_inputclk clksrc = {.clk = 24000000, .div = 16};
HWIATTR_UART_SET_NUM_IRQ(&attr, 1);
HWIATTR_UART_SET_NUM_CLK(&attr, 1);
/* create uart0 */
HWIATTR_UART_SET_LOCATION(&attr, AW_H3_UART0_BASE, AW_H3_UART_SIZE, 0, hwi_find_as(AW_H3_UART0_BASE, 1));
hwi_off = hwidev_add_uart("uart", &attr, hwi_bus_internal);
ASSERT(hwi_find_unit(hwi_off) == 0);
hwitag_set_ivec(hwi_off, 0, AW_H3_UART0_IRQ);
hwitag_set_inputclk(hwi_off, 0, &clksrc);
/* historically the UART's were called 'omap' so add these synonyms */
hwi_add_synonym(hwi_find_device("uart", 0), "seromap");
}
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Allwinner H3 Generic Interrupt Controller support.
*/
#include "startup.h"
#include <arm/gic.h>
#include <arm/aw_h3.h>
static paddr_t aic_base = AW_H3_GIC_BASE;
const static struct startup_intrinfo intrs[] = {
/* ARM General Interrupt Controller */
{ .vector_base = _NTO_INTR_CLASS_EXTERNAL,
.num_vectors = 157,
.cascade_vector = _NTO_INTR_SPARE,
.cpu_intr_base = 0,
.cpu_intr_stride = 0,
.flags = 0,
.id = { INTR_GENFLAG_LOAD_SYSPAGE, 0, &interrupt_id_gic },
.eoi = { INTR_GENFLAG_LOAD_SYSPAGE | INTR_GENFLAG_LOAD_INTRMASK, 0, &interrupt_eoi_gic },
.mask = &interrupt_mask_gic,
.unmask = &interrupt_unmask_gic,
.config = &interrupt_config_gic,
.patch_data = &aic_base,
},
};
void
init_intrinfo()
{
kprintf("Initializing GIC...\n");
unsigned gic_dist = AW_H3_GICD_BASE;
unsigned gic_cpu = AW_H3_GICC_BASE;
/*
* Initialise GIC distributor and our cpu interface
*/
arm_gic_init(gic_dist, gic_cpu);
add_interrupt_array(intrs, sizeof(intrs));
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Allwinner H3 system timer support.
* Used generic ARMv7 Global Timer
*/
#include "startup.h"
extern unsigned armv7gt_cntfrq;
/*
* The CNTFRQ is a Generic Timer register, it indicates the system counter clock frequency in Hz.
*/
static unsigned
timer_read_cntfrq_v7gt()
{
unsigned frq;
__asm__ __volatile__("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
return frq;
}
void
init_qtime()
{
kprintf("Initializing Timer...\n");
armv7gt_cntfrq = timer_read_cntfrq_v7gt();
init_qtime_v7gt();
}

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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* init_raminfo.c
* Tell syspage about our RAM configuration
*/
#include "startup.h"
#include "board.h"
void init_raminfo()
{
kprintf("Initializing RAM...\n");
add_ram(AW_H3_RAM_BASE, MEG(ORANGEPI_PC_RAM_SIZE));
}

136
src/hardware/startup/boards/orangepi/main.c Обычный файл
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/*
* (c) 2023, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* Startup for OrangePi PC Allwinner H3 (ARMv7 Cortex-A7 QuadCore)
*/
#include "startup.h"
#include "board.h"
#include "aw_h3_startup.h"
const struct callout_slot callouts[] = {
{ CALLOUT_SLOT(reboot, _awh3) },
};
/* The USB-Serial is on UART_0 */
const struct debug_device debug_devices[] = {
{ "8250",
{ "0x01C28000^2.0.24000000.16", // UART0, use the baud rate set by boot loader
},
init_omap,
put_omap,
{ &display_char_8250,
&poll_key_8250,
&break_detect_8250,
}
},
};
/*
* main()
* Startup program executing out of RAM
*
* 1. It gathers information about the system and places it in a structure
* called the system page. The kernel references this structure to
* determine everything it needs to know about the system. This structure
* is also available to user programs (read only if protection is on)
* via _syspage->.
*
* 2. It (optionally) turns on the MMU and starts the next program
* in the image file system.
*/
int
main(int argc, char **argv, char **envv)
{
int opt;
while ((opt = getopt(argc, argv, COMMON_OPTIONS_STRING)) != -1) {
handle_common_option(opt);
}
/*
* Initialize debugging output
*/
select_debug(debug_devices, sizeof(debug_devices));
kprintf("Welcome to KPDA Neutrino startup on OrangePi PC Allwinner H3 (ARMv7 Cortex-A7 QuadCore)\n");
kprintf("Initializing Debug Port...\n");
add_callout_array(callouts, sizeof(callouts));
/*
* Collect information on all free RAM in the system
*/
init_raminfo();
/*
* Remove RAM used by modules in the image
*/
alloc_ram(shdr->ram_paddr, shdr->ram_size, 1);
/*
* Initialize SMP
*/
aw_h3_spinlock_init();
aw_h3_timer_init();
init_smp();
/*
* Initialize MMU
*/
if (shdr->flags1 & STARTUP_HDR_FLAGS1_VIRTUAL)
{
init_mmu();
kprintf("Initializing MMU...\n");
}
/* Initialize the Interrupts related Information */
init_intrinfo();
/* Initialize the Timer related information */
init_qtime();
/* Init L2 Cache Controller */
init_cacheattr();
/* Initialize the CPU related information */
init_cpuinfo();
/* Initialize the Hwinfo section of the Syspage */
init_hwinfo();
add_typed_string(_CS_MACHINE, "OrangePi PC");
/*
* Load bootstrap executables in the image file system and Initialise
* various syspage pointers. This must be the _last_ initialisation done
* before transferring control to the next program.
*/
init_system_private();
/*
* This is handy for debugging a new version of the startup program.
* Commenting this line out will save a great deal of code.
*/
print_syspage();
kprintf("Jumping to KPDA\n");
return 0;
}

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define PINFO
PINFO DESCRIPTION=OrangePi-PC Allwinner-H3 ARMv7 Cortex-A7 QuadCore startup
endef

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@page "startup-orangepi" startup-orangepi
@brief Модуль инициализации и запуска системы OrangePi-PC Allwinner-H3
@remark startup-orangepi [универсальные опции библиотеки libstartup]
@par Платформы:
ЗОСРВ «Нейтрино»
@arch{armv7}
@par Опции:
Все модули инициализации систем в ЗОСРВ «Нейтрино» слинкованы с одной из стандартных библиотек @a libstartup и поддерживают её набор универсальных опций. Также у любого из них могут существовать дополнительные эксклюзивные опции. Ниже рассматриваются универсальные опции библиотек:
@caution
Различные модули инициализации могут перекрывать универсальные опции, а также поддерживать дополнительные, специфичные для конкретных систем, опции. Приоритет действия следующий:
@ol
@item Опции модулей инициализации для конкретных архитектур/систем.
@item Опции библиотеки для конкретных архитектур.
@item Универсальные опции библиотеки.
@endol
@endcaution
@par Универсальные опции библиотеки libstartup
Стандартные опции библиотеки libstartup описаны на странице описания модуля @l{startup-*|startup} в разделе @l{startup-*|Универсальные опции библиотеки libstartup}.
@par Описание:
Модуль инициализации @a startup-orangepi обеспечивает запуск и начальную инициализацию отладочной платы OrangePi-PC на базе микропроцессора Allwinner-H3.
@par Примеры:
Базовый вариант запуска с включением вывода отладочной информации:
@code
startup-orangepi -v
@endcode
@par Классификация:
Базовые подсистемы ЗОСРВ «Нейтрино», Драйверы
@prev{./10-Components.html|table_of_drivers||1}

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src/hardware/startup/lib/Makefile Обычный файл
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LIST=CPU
include recurse.mk

36
src/hardware/startup/lib/__main.c Обычный файл
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/*
* (c) 2010-2014, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
/*
* Keep the GNU compiler happy with this - used for C++ initialization
* in another world.
*/
void __main(void)
{
}

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src/hardware/startup/lib/_init_ssp.c Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2007, QNX Software Systems. All Rights Reserved.
*
* You must obtain a written license from and pay applicable license fees to QNX
* Software Systems before you may reproduce, modify or distribute this software,
* or any work that includes all or part of this software. Free development
* licenses are available for evaluation and non-commercial purposes. For more
* information visit http://licensing.qnx.com or email licensing@qnx.com.
*
* This file may contain contributions from others. Please review this entire
* file for other proprietary rights or license notices, as well as the QNX
* Development Suite License Guide at http://licensing.qnx.com/license-guide/
* for other information.
* $
*/
#include <stdint.h>
void *__stack_chk_guard;
void __init_stack_guard(void) {
// Dummy version to override the one in libc, since it makes use
// of operating system services that aren't available in startup.
}

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src/hardware/startup/lib/_main.c Обычный файл
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/*
* (c) 2010-2017, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
unsigned paddr_bits = 32;
int debug_flag = 0;
unsigned reserved_size;
unsigned reserved_align;
unsigned long cpu_freq;
unsigned long cycles_freq;
unsigned long timer_freq;
chip_info dbg_device[2];
unsigned patch_channel;
struct startup_header *shdr;
char **_argv;
int _argc;
unsigned max_cpus = PROCESSORS_MAX;
unsigned system_icache_idx = CACHE_LIST_END;
unsigned system_dcache_idx = CACHE_LIST_END;
chip_info timer_chip;
unsigned (*timer_start)(void);
unsigned (*timer_diff)(unsigned start);
struct syspage_entry *_syspage_ptr;
unsigned misc_flags;
int secure_system = 0;
extern struct bootargs_entry boot_args; //filled in by mkifs
extern int main(int argc,char **argv,char **envv);
static char *argv[20], *envv[20];
static void
setup_cmdline(void) {
char *args;
int i, argc, envc;
//
// Find and construct argument and environment vectors for ourselves
//
tweak_cmdline(&boot_args, "startup");
argc = envc = 0;
args = boot_args.args;
for(i = 0; i < boot_args.argc; ++i) {
if(i < (int)(sizeof(argv)/sizeof(*argv)-1)) argv[argc++] = args;
while(*args++) ;
}
argv[argc] = 0;
for(i = 0; i < boot_args.envc; ++i) {
if (i < (int)(sizeof(envv)/sizeof(*envv)-1)) envv[envc++] = args;
while(*args++) ;
}
envv[envc] = 0;
_argc = argc;
_argv = argv;
}
void
_main(void) {
void *syspage_mem = NULL;
shdr = (struct startup_header *)boot_args.shdr_addr;
board_init();
setup_cmdline();
cpu_startup();
#define INIT_SYSPAGE_SIZE 0x800
syspage_mem = ws_alloc(INIT_SYSPAGE_SIZE);
if(!syspage_mem) {
crash("No memory for syspage.\n");
}
init_syspage_memory(syspage_mem, INIT_SYSPAGE_SIZE);
if(shdr->imagefs_paddr != 0) {
avoid_ram(shdr->imagefs_paddr, shdr->stored_size);
}
main(_argc, _argv, envv);
//
// Tell the mini-drivers that the next time they're called, they're
// going to be in the kernel. Also flip the handler & data pointers
// to the proper values for that environment.
//
mdriver_hook();
//
// Copy the local version of the system page we've built to the real
// system page location we allocated in init_system_private().
//
write_syspage_memory();
//
// Tell the AP's that that the syspage is now present.
//
smp_hook_rtn();
startnext();
}
static void
hook_dummy(void) {
}
void (*smp_hook_rtn)(void) = hook_dummy;
void (*mdriver_check)(void) = hook_dummy;
void (*mdriver_hook)(void) = hook_dummy;
// Replacement for some C library stuff to minimize startup size
int errno;
int *
__get_errno_ptr(void) { return &errno; }
size_t
__stackavail(void) { return (size_t)~0; }
void
abort(void) { crash("ABORT"); for( ;; ) {} }

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src/hardware/startup/lib/acpi.c Обычный файл
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/*
* (c) 2010-2014, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
#include <hw/acpi.h>
paddr_t
acpi_find_table_next(unsigned table_name, unsigned *lenp, paddr_t start_search) {
static unsigned num_tbls = -1;
static paddr_t *tbl_array;
paddr_t tbl_paddr;
acpi_rsdp *root;
acpi_generic *tbl;
unsigned i;
unsigned sig;
if(num_tbls == 0) {
return NULL_PADDR;
}
if(tbl_array == NULL) {
root = board_find_acpi_rsdp();
if(root == NULL) {
num_tbls = 0;
return NULL_PADDR;
}
if((root->v1.Revision == ACPI_RSDP_REVISION_1_0) || (root->XsdtAddress == 0)) {
if((root->v1.Revision != ACPI_RSDP_REVISION_1_0) && (debug_flag > 0)) {
kprintf("ACPI rev %d, XsdtAddress not set, use RsdtAddress\n", root->v1.Revision);
}
tbl_paddr = root->v1.RsdtAddress;
startup_memory_unmap(root);
tbl = startup_memory_map(0x4096, tbl_paddr, PROT_READ);
num_tbls = (tbl->hdr.Length - offsetof(acpi_rsdt, Entry)) / sizeof(tbl->rsdt.Entry[0]);
tbl_array = ws_alloc(num_tbls * sizeof(*tbl_array));
for(i = 0; i < num_tbls; ++i) {
tbl_array[i] = tbl->rsdt.Entry[i];
}
} else {
tbl_paddr = root->XsdtAddress;
startup_memory_unmap(root);
tbl = startup_memory_map(0x4096, tbl_paddr, PROT_READ);
num_tbls = (tbl->hdr.Length - offsetof(acpi_xsdt, Entry)) / sizeof(tbl->xsdt.Entry[0]);
tbl_array = ws_alloc(num_tbls * sizeof(*tbl_array));
for(i = 0; i < num_tbls; ++i) {
tbl_array[i] = tbl->xsdt.Entry[i];
}
}
startup_memory_unmap(tbl);
}
int searching = (start_search == NULL_PADDR);
for(i = 0; i < num_tbls; ++i) {
tbl_paddr = tbl_array[i];
if(searching) {
tbl = startup_memory_map(sizeof(*tbl), tbl_paddr, PROT_READ);
sig = tbl->hdr.Signature;
if(lenp != NULL) {
*lenp = tbl->hdr.Length;
}
startup_memory_unmap(tbl);
if(sig == table_name) {
return tbl_paddr;
}
} else if(start_search == tbl_paddr) {
searching = 1;
}
}
return NULL_PADDR;
}
paddr_t
acpi_find_table(unsigned table_name, unsigned *lenp) {
return acpi_find_table_next(table_name, lenp, NULL_PADDR);
}

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src/hardware/startup/lib/add_cache.c Обычный файл
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/*
* (c) 2010-2014, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
static output_callout_t *cache_prev_output_rtn;
static output_callout_t *
callout_output_cache(int sizing) {
unsigned i;
unsigned num_cache;
num_cache = lsp.cacheattr.size / sizeof(*lsp.cacheattr.p);
for(i = 0; i < num_cache; ++i) {
struct cacheattr_entry *cache = &lsp.cacheattr.p[i];
callout_output_one(sizing, &cache->control);
}
return(cache_prev_output_rtn);
}
int
add_cache_ways(const unsigned next, const unsigned flags, const unsigned line_size, const unsigned num_lines,
const unsigned ways, const struct callout_rtn *rtn) {
struct cacheattr_entry *cache = lsp.cacheattr.p;
int num = lsp.cacheattr.size / sizeof(*cache);
int i;
if(cache_prev_output_rtn == NULL) {
//Hook into the sizing/writing list
cache_prev_output_rtn = callout_output_rtn;
callout_output_rtn = (output_callout_t *)callout_output_cache;
}
//Look for an already existing entry that matches
for(i = 0; i < num; ++i, ++cache) {
if( cache->next == next
&& cache->flags == flags
&& cache->line_size == line_size
&& cache->num_lines == num_lines
&& cache->control == (cache_rtn *)rtn) return(i);
}
//Have to add a new entry
cache = grow_syspage_section(&lsp.cacheattr, sizeof(*cache));
cache += i;
cache->next = next;
cache->flags = flags;
cache->line_size = line_size;
cache->num_lines = num_lines;
cache->ways = ways;
cache->control = (cache_rtn *)rtn;
return(i);
}
int
add_cache(const unsigned next,const unsigned flags, const unsigned line_size, const unsigned num_lines,
const struct callout_rtn *rtn) {
return add_cache_ways(next, flags, line_size, num_lines, 0, rtn);
}

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src/hardware/startup/lib/add_interrupt.c Обычный файл
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/*
* (c) 2010-2018, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
//
// This code is hardware independant and should not have to be
// changed by end users.
//
static const uint8_t offsets[] = {
offsetof(struct intrinfo_entry, id.rtn),
offsetof(struct intrinfo_entry, eoi.rtn),
offsetof(struct intrinfo_entry, mask),
offsetof(struct intrinfo_entry, unmask),
offsetof(struct intrinfo_entry, config),
};
static output_callout_t *intr_prev_output_rtn;
static output_callout_t *
callout_output_intr(int sizing) {
unsigned i;
unsigned nelts;
nelts = lsp.intrinfo.size / sizeof(*lsp.intrinfo.p);
for(i = 0; i < nelts; ++i) {
uint8_t *base = (uint8_t *)&lsp.intrinfo.p[i];
unsigned j;
for(j = 0; j < NUM_ELTS(offsets); ++j) {
void (**rtn)(void) = (void (**)(void))(base + offsets[j]);
callout_output_one(sizing, rtn);
}
}
return(intr_prev_output_rtn);
}
struct intrinfo_entry *
add_interrupt(const struct startup_intrinfo *startup_intr) {
struct intrinfo_entry *intr;
unsigned i;
if(intr_prev_output_rtn == NULL) {
//Hook into the sizing/writing list
intr_prev_output_rtn = callout_output_rtn;
callout_output_rtn = (output_callout_t *)callout_output_intr;
}
intr = grow_syspage_section(&lsp.intrinfo, sizeof(*intr));
//Point at newly allocated entry
intr = (void *)((uint8_t *)intr + lsp.intrinfo.size - sizeof(*intr));
*intr = *(struct intrinfo_entry *)startup_intr;
// Cleanup a garbage
memset((void *)intr + sizeof(struct startup_intrinfo), 0, sizeof(struct intrinfo_entry) - sizeof(struct startup_intrinfo));
if(startup_intr->id.rtn != NULL) {
intr->id.size = startup_intr->id.rtn->rtn_size;
}
if(startup_intr->eoi.rtn != NULL) {
intr->eoi.size = startup_intr->eoi.rtn->rtn_size;
}
for(i = 0; i < NUM_ELTS(offsets); ++i) {
void (**rtn)(void) = (void (**)(void))((uintptr_t)intr + offsets[i]);
callout_register_data(rtn, startup_intr->patch_data);
}
return(intr);
}
void
add_interrupt_array(const struct startup_intrinfo *intrs, unsigned size) {
unsigned i;
unsigned incr;
incr = sizeof(*intrs);
//
//Backwards compatability stuff - can be removed once
//all the startups have been recompiled with the new startup_intrinfo
//structure
//
if((size % sizeof(*intrs)) != 0) {
incr -= sizeof(void *);
}
for(i = size / incr; i > 0; --i) {
add_interrupt(intrs);
intrs = (void *)((uintptr_t)intrs + incr);
}
}

50
src/hardware/startup/lib/alloc_qtime.c Обычный файл
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/*
* (c) 2010-2014, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
/*
* alloc_qtime()
* Allocate the qtime section and initialize the boot time from the
* IPL info or an RTC chip.
*/
struct qtime_entry *
alloc_qtime() {
struct qtime_entry *qtime = set_syspage_section(&lsp.qtime, sizeof(*lsp.qtime.p));
const struct startup_info_time *time;
qtime->epoch = 1970;
if(!(misc_flags & MISC_FLAG_SUPPRESS_BOOTTIME)) {
time = find_startup_info(NULL, STARTUP_INFO_TIME);
qtime->boot_time = (time != NULL) ? time->time : rtc_time();
qtime->nsec_tod_adjust = qtime->boot_time * (uint64_t)1000000000;
}
return(qtime);
}

35
src/hardware/startup/lib/ap_fail.c Обычный файл
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/*
* (c) 2010-2014, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
void
ap_fail(int cpu) {
/* we crash in the case of an AP failing to start. */
crash("CPU %d start failure\n", cpu);
}

2
src/hardware/startup/lib/arm/Makefile Обычный файл
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LIST=VARIANT
include recurse.mk

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@ -0,0 +1 @@
include ../../common.mk

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2010, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
/*
* This is already defined in a libc. We are temporarily defining it here
* in order to not break bsp builds because they pick up the libc.a from the
* installed sdp rather than the one that matches the startup source.
*/
unsigned __clockcycles_incr_bit;
static output_callout_t *prev_output_rtn;
static output_callout_t *
callout_output_clock(int sizing)
{
struct arm_cpu_entry *cpu = lsp.cpu.arm_cpu.p;
callout_output_one(sizing, &cpu->clock_cycles);
return prev_output_rtn;
}
void
arm_add_clock_cycles(struct callout_rtn *callout, int incr_bit)
{
struct arm_cpu_entry *cpu = lsp.cpu.arm_cpu.p;
if (prev_output_rtn == 0) {
prev_output_rtn = callout_output_rtn;
callout_output_rtn = (output_callout_t *)callout_output_clock;
}
cpu->clock_cycles = (void *)callout;
if (incr_bit == 32) {
__clockcycles_incr_bit = 32;
} else {
__clockcycles_incr_bit = 0;
}
}

258
src/hardware/startup/lib/arm/arm_cache.c Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
static inline unsigned
arm_v7_ccsidr(int level, int icache)
{
unsigned ccsidr;
// Set CSSELR for this level and cache type
__asm__ __volatile__("mcr p15, 2, %0, c0, c0, 0" : : "r"((level << 1) | icache));
// Get CSSIDR value
__asm__ __volatile__("mrc p15, 1, %0, c0, c0, 0" : "=r"(ccsidr));
return ccsidr;
}
static inline void
arm_v7_cache_size(unsigned cssidr, unsigned *nline, unsigned *lsize)
{
unsigned nsets = ((cssidr >> 13) & 0x7fff) + 1;
unsigned assoc = ((cssidr >> 3) & 0x3ff) + 1;
*nline = nsets * assoc;
*lsize = 1 << ((cssidr & 7) + 4);
}
void
arm_v7_add_cache(unsigned cpunum, struct cpuinfo_entry *cpu, const struct armv_cache *cache)
{
unsigned clidr;
int i;
/*
* Read CLIDR to figure out how many cache levels are implemented
*/
__asm__ __volatile__("mrc p15, 1, %0, c0, c0, 1" : "=r"(clidr));
for (i = 0; i < 8; i++, clidr >>= 3) {
unsigned type = clidr & 7;
unsigned ccsidr;
unsigned nline = 0;
unsigned lsize = 0;
unsigned flags;
if (type == 0) {
break;
}
if (type > 4) {
crash("CLIDR reports reserved value");
}
flags = 0;
if (type & 1) {
ccsidr = arm_v7_ccsidr(i, 1);
arm_v7_cache_size(ccsidr, &nline, &lsize);
if (debug_flag) {
kprintf("CPU%d: L%d Icache: %dx%d\n", cpunum, i+1, nline, lsize);
}
/*
* FIXME: do we need to check CTR to set CACHE_FLAG_VIRTUAL?
*/
flags = CACHE_FLAG_INSTR;
/*
* CP15 cache operations work on all levels so only call add_cache()
* for L1 caches.
*/
if (i == 0) {
cpu->ins_cache = add_cache(cpu->ins_cache,
flags,
lsize,
nline,
cache->icache_rtn);
}
}
if ((type & 2) || type == 4) {
ccsidr = arm_v7_ccsidr(i, 0);
arm_v7_cache_size(ccsidr, &nline, &lsize);
flags = (type == 4) ? CACHE_FLAG_UNIFIED : CACHE_FLAG_DATA;
if (ccsidr & (1 << 30)) {
flags |= CACHE_FLAG_WRITEBACK;
}
if (debug_flag) {
kprintf("CPU%d: L%d Dcache: %dx%d %s\n", cpunum, i+1, nline, lsize, (flags & CACHE_FLAG_WRITEBACK) ? "WB" : "WT");
}
/*
* CP15 cache operations work on all levels so only call add_cache()
* for L1 caches.
*/
if (i == 0) {
cpu->data_cache = add_cache(cpu->data_cache,
flags,
lsize,
nline,
cache->dcache_rtn);
}
}
}
}
/*
* Parse the CP15 cache type register
*/
static void
arm_cache_size(unsigned csize, unsigned *nline, unsigned *lsize)
{
unsigned S = (csize >> 6) & 15;
unsigned A = (csize >> 3) & 7;
unsigned M = (csize >> 2) & 1;
unsigned L = (csize & 3) + 3;
/*
* Check if cache is absent
*/
if (A == 0 && M == 1) {
*nline = 0;
*lsize = 0;
}
else {
*nline = (M+2) << (S + 8 - L);
*lsize = 1 << L;
}
}
void
arm_add_cache(struct cpuinfo_entry *cpu, const struct armv_cache *cache)
{
unsigned ctype;
unsigned nline;
unsigned lsize;
unsigned flags;
unsigned cpunum = cpu - lsp.cpuinfo.p;
/*
* Use hardcoded values if there is no cache type register
*/
if (cache->dcache_config || cache->icache_config) {
const struct arm_cache_config *config;
if (config = cache->dcache_config) {
cpu->data_cache = add_cache(cpu->data_cache,
config->flags,
config->line_size,
config->num_lines,
cache->dcache_rtn);
if (debug_flag) {
kprintf("CPU%d: %s: %dx%d %s\n", cpunum, (config->flags & CACHE_FLAG_INSTR) ? "Cache" : "Dcache", config->num_lines, config->line_size, (config->flags & CACHE_FLAG_WRITEBACK) ? "WB" : "WT");
}
}
if (config = cache->icache_config) {
cpu->ins_cache = add_cache(cpu->ins_cache,
config->flags,
config->line_size,
config->num_lines,
cache->icache_rtn);
if (debug_flag) {
kprintf("CPU%d: Icache: %dx%d\n", cpunum, config->num_lines, config->line_size);
}
}
return;
}
/*
* Read CP15 cache type register
*/
ctype = arm_mmu_cache_type();
if (ctype & (1U << 31)) {
/*
* ARMv7 cache handling is different
*/
arm_v7_add_cache(cpunum, cpu, cache);
return;
}
/*
* Get Data/Unified cache size
*/
arm_cache_size(ctype >> 12, &nline, &lsize);
#ifndef FIXME
if (nline == 0)
crash("No Dcache in cache type register?");
#endif
/*
* FIXME: currently all ARM caches are virtual - this may change
*/
flags = CACHE_FLAG_VIRTUAL;
if (((ctype >> 25) & 15) != 0)
flags |= CACHE_FLAG_WRITEBACK;
if ((ctype & (1 << 24)) == 0) {
flags |= CACHE_FLAG_UNIFIED;
}
else {
flags |= CACHE_FLAG_DATA;
}
if (debug_flag) {
kprintf("CPU%d: %s: %dx%d %s\n", cpunum, (flags & CACHE_FLAG_INSTR) ? "Cache" : "Dcache", nline, lsize, (flags & CACHE_FLAG_WRITEBACK) ? "WB" : "WT");
}
cpu->data_cache = add_cache(cpu->data_cache, flags, lsize, nline, cache->dcache_rtn);
if ((flags & CACHE_FLAG_INSTR) == 0) {
/*
* Get Instruction cache size
*/
arm_cache_size(ctype, &nline, &lsize);
#ifndef FIXME
if (nline == 0)
crash("No Icache in cache type register?");
#endif
if (debug_flag) {
kprintf("CPU%d: Icache: %dx%d\n", cpunum, nline, lsize);
}
/*
* FIXME: currently all ARM caches are virtual - this may change
*/
flags = CACHE_FLAG_VIRTUAL | CACHE_FLAG_INSTR;
cpu->ins_cache = add_cache(cpu->ins_cache, flags, lsize, nline, cache->icache_rtn);
}
}

132
src/hardware/startup/lib/arm/arm_cache_mmu.S Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2013 QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
.text
.align 2
.globl arm_enable_mmu
.globl arm_mp_cpuid
.globl arm_v7_enable_cache
.globl arm_v7_disable_cache_mmu
/*
* r0: the address holds the translation table which is supposed
* to have been filled properly
* Assume both i-cache and d-cache are clean
*/
arm_enable_mmu:
mov r1, #0
mcr p15, 0, r1, c8, c7, 0 // invalidate TLBs
dsb
isb
mov r1, #0
mcr p15, 0, r1, c2, c0, 2 // Always use TTBR0
/*
* Set the translation table base
*/
orr r0, r0, #((3 << 3) | 3)
mcr p15, 0, r0, c2, c0, 0
/*
* Enable MMU domain 15
*/
mov r0, #(1 << 30) // Client mode
mcr p15, 0, r0, c3, c0, 0
/* Enable I/D cache, Enable MMU*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(1 << 0) // enable MMU
mcr p15, 0, r0, c1, c0, 0
dsb
isb
mov pc, lr
/*
* Supposed to be call if Multiprocessor ID Register is supported
*/
arm_mp_cpuid:
mrc p15, 0, r0, c0, c0, 5
ands r0, r0, #0x03
mov pc, lr
arm_v7_enable_cache:
stmfd r13!, {r4, r12, r14}
/* invalidation i-cache and d-cache before enabling them */
bl arm_v7_icache_invalidate
bl arm_v7_dcache_flush
/*
* Enable I/D cache
*/
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(1 << 12) // enable I Cache
orr r0, r0, #(1 << 2) // enable D Cache
mcr p15, 0, r0, c1, c0, 0
dsb
isb
ldmfd r13!, {r4, r12, pc}
arm_v7_disable_cache_mmu:
stmdb sp!,{lr}
mrc p15, 0, lr, c1, c0, 0
tst lr, #0x05 // MMU/D-cache enabled?
ldmeqia sp!, {pc}
/*
* Flush D-cache
*/
bl arm_v7_dcache_flush
/*
* Turn off MMU and data cache if necessary.
* WARNING: assumes we are running with a 1-1 mapping if MMU is enabled.
*/
mrc p15, 0, ip, c1, c0, 0
bic ip, ip, #0x00002000 // clear bits 13 (--V-)
bic ip, ip, #0x00001000 // clear bit 1 (i-cache)
bic ip, ip, #0x00000007 // clear bits 2:0 (-CAM)
mcr p15, 0, ip, c1, c0, 0
dsb
isb
/*
* Invalidate caches and TLBs.
*/
mov ip, #0
mcr p15, 0, ip, c8, c7, 0 // invalidate TLBs
mcr p15, 0, ip, c7, c5, 0 // invalidate icache
dsb
isb
ldmia sp!,{pc}

90
src/hardware/startup/lib/arm/arm_cpuspeed.c Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
int cycles_per_loop;
static void inline
loop(unsigned count) {
volatile unsigned tmp = count;
__asm__ __volatile__(
"1: subs %0, %0, #1;"
" bgt 1b"
:
: "r" (tmp)
);
}
unsigned long
arm_cpuspeed()
{
unsigned speed;
unsigned adjust;
int change;
unsigned start;
unsigned diff;
unsigned one_ms;
unsigned upwards;
upwards = 0;
adjust = 1000;
speed = 1000;
change = 1000;
one_ms = timer_ns2tick(1000000000UL/1000);
for( ;; ) {
start = timer_start();
loop(speed);
diff = timer_diff(start);
if(diff <= one_ms) {
if(change < 0) adjust /= 2;
change = adjust;
if(diff < one_ms && change == 0) change = 1;
++upwards;
} else {
if(change > 0) adjust /= 2;
change = -adjust;
upwards = 0;
}
if(change == 0) break;
if((diff == 0) && (upwards > 100)) {
crash("Timer not running. Possible configuration problem?\n");
}
speed += change;
}
/*
* Multiply by 3.01 and divide by 1000 to get MHz:
* - 3.00 => cycles per loop
* - 0.01 => error correction
*/
speed = ((speed * cycles_per_loop) + (speed/100)) / 1000;
return speed;
}

130
src/hardware/startup/lib/arm/arm_gic.c Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2011, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
#include <arm/gic.h>
paddr_t gic_dist_base;
paddr_t gic_cpu_base;
/*
* Use inline assembly to prevent the compile from generating
* writeback register increment code, which causes data abort
* fault with hypervisor.
*/
static __inline__ void __attribute__((__unused__))
no_writeback_out32(uintptr_t __addr, uint32_t __data)
{
__asm__ __volatile__ ("str %1, %0"
: "+Qo" (*(volatile uint32_t *)__addr)
: "r" (__data));
}
void
arm_gic_init(paddr_t dist_base, paddr_t cpu_base)
{
unsigned i;
unsigned itn;
gic_dist_base = dist_base;
gic_cpu_base = cpu_base;
/*
* Make sure distributor is disabled
*/
no_writeback_out32(dist_base + ARM_GICD_CTLR, 0);
/*
* Calculate number of interrupt lines
*/
itn = ((in32(dist_base + ARM_GICD_TYPER) & ARM_GICD_TYPER_ITLN) + 1) * 32;
/*
* Disable all interrupts and clear pending state
*/
for (i = 0; i < itn; i += 32) {
no_writeback_out32(dist_base + ARM_GICD_ICENABLERn + (i * 4 / 32), 0xffffffff);
no_writeback_out32(dist_base + ARM_GICD_ICPENDRn + (i * 4 / 32), 0xffffffff);
}
/*
* Set default priority of all interrupts to 0xa0
*/
for (i = 0; i < itn; i += 4) {
no_writeback_out32(dist_base + ARM_GICD_IPRIORITYn + i, 0xa0a0a0a0);
}
/*
* Route all SPI interrupts to cpu0
*/
for (i = 32; i < itn; i += 4) {
no_writeback_out32(dist_base + ARM_GICD_ITARGETSRn + i, 0x01010101);
}
/*
* Default all SPI interrupts as level triggered
*/
for (i = 32; i < itn; i += 16) {
no_writeback_out32(dist_base + ARM_GICD_ICFGRn + (i * 4 / 16), 0);
}
/*
* Enable distributor
*/
no_writeback_out32(dist_base + ARM_GICD_CTLR, ARM_GICD_CTLR_EN);
/*
* Enable cpu interface for cpu0.
* Secondary cpu interfaces are enables as those cpus are initialised
*/
arm_gic_cpu_init();
}
void
arm_gic_cpu_init()
{
if (gic_dist_base == 0 || gic_cpu_base == 0) {
crash("gic not initialised");
}
/*
* Disable all banked PPI interrupts
* Enable all SGI interrupts
*/
out32(gic_dist_base + ARM_GICD_ICENABLERn, 0xffff0000);
out32(gic_dist_base + ARM_GICD_ISENABLERn, 0x0000ffff);
/*
* Set priority mask to allow all interrupts and enable cpu interface
*/
out32(gic_cpu_base + ARM_GICC_PMR, 0xF0);
out32(gic_cpu_base + ARM_GICC_CTLR, ARM_GICC_CTLR_EN);
}
int
arm_gic_num_spis(void)
{
return ((in32(gic_dist_base + ARM_GICD_TYPER) & ARM_GICD_TYPER_ITLN) + 1) * 32;
}

306
src/hardware/startup/lib/arm/arm_map.c Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
// As paddrs are cast to pointers, it is assumed that L1s and L2s are allocated from memory < 4G
#define CPU_L1_TABLE(cpu) ((uintptr_t)((L1_paddr + ((cpu) * ARM_L1_SIZE)) & ~ARM_TTBR_ATTR_MASK))
#define CPU_L2_TABLE(cpu) ((uintptr_t)(L2_paddr + ((cpu) * __PAGESIZE)))
static paddr32_t
set_prot(paddr32_t paddr, int flags)
{
if (flags == ARM_MAP_SYSPAGE) {
if (arm_v6_mmu) {
/*
* WARNING: we assume user RW has APX/AP1/AP0=011:
* - by clearing AP0 we can set user RO/priv RW
* - we need to clear nG so it doesn't use an ASID
*/
paddr |= armv_pte->upte_rw;
paddr &= ~(ARM_PTE_V6_AP0 | ARM_PTE_V6_nG);
}
else {
/*
* user RO allows privileged RW access on non-ARMv6 cpus
*/
paddr |= armv_pte->upte_ro;
}
return paddr;
}
if (flags & ARM_PTE_U) {
paddr |= (flags & ARM_PTE_RW) ? armv_pte->upte_rw
: armv_pte->upte_ro;
}
else {
paddr |= (flags & ARM_PTE_RW) ? armv_pte->kpte_rw
: armv_pte->kpte_ro;
}
if ((flags & ARM_PTE_CB) != ARM_PTE_CB) {
paddr &= ~armv_pte->mask_nc;
}
if (arm_v6_mmu) {
paddr |= (flags & (ARM_PTE_V6_S|ARM_PTE_V6_SP_TEX_MASK|ARM_PTE_CB));
if (flags & ARM_MAP_NOEXEC) {
paddr |= ARM_PTE_V6_SP_XN;
}
} else {
paddr |= (flags & (ARM_PTE_V5_SP_TEX_MASK|ARM_PTE_CB));
}
return paddr;
}
/*
* Map a 4K page table into "page directory" and L1 table for specified cpu
* Each L2 is 1k; this carves one page into 4 L2 tables and points 4 L1 entries appropriately
*/
static void
map_ptbl_cpu(int cpu, paddr32_t ptbl, uintptr_t vaddr)
{
pte_t *pte = (pte_t *)CPU_L2_TABLE(cpu) + (vaddr >> 22); // 1mb per page dir
ptp_t *ptp = (ptp_t *)CPU_L1_TABLE(cpu) + ((vaddr >> 20) & ~3);
int i;
/*
* Map the page table into the "page directory" page table
*/
*pte = ((ptbl | armv_pte->kpte_rw) & ~armv_pte->mask_nc) | armv_chip->pte_attr;
/*
* Map the page table into the L1 table
*/
for (i = 0; i < 4; i++, ptbl += ARM_L2_SIZE) {
*ptp++ = ptbl | armv_pte->l1_pgtable; // 1k each, so four consecutive l1 entries
}
}
/*
* Map a 4K page table into "page directory" and L1 table on all cpus
*/
void
map_ptbl(paddr32_t pt, uintptr_t vaddr)
{
int cpu;
for (cpu = 0; cpu < lsp.syspage.p->num_cpu; cpu++) {
map_ptbl_cpu(cpu, pt, vaddr);
}
}
/*
* Map the "page directory" page for each CPU
*/
void
arm_pdmap(uintptr_t vaddr)
{
int cpu;
for (cpu = 0; cpu < lsp.syspage.p->num_cpu; cpu++) {
map_ptbl_cpu(cpu, CPU_L2_TABLE(cpu), vaddr);
}
}
/*
* Map a 1MB section into the L1 table.
*/
void
arm_scmap(uintptr_t vaddr, paddr32_t paddr, int flags)
{
unsigned prot = (flags & ARM_PTE_RW) ? armv_pte->kscn_rw : armv_pte->kscn_ro;
unsigned cpu;
if (flags & ARM_PTE_CB) {
prot |= armv_pte->kscn_cb;
}
for (cpu = 0; cpu < lsp.syspage.p->num_cpu; cpu++) {
ptp_t *ptp = (ptp_t *)CPU_L1_TABLE(cpu) + (vaddr >> 20);
*ptp = paddr | prot;
}
}
/*
* Unmap section entry
*/
void
arm_scunmap(uintptr_t vaddr)
{
unsigned cpu;
for (cpu = 0; cpu < lsp.syspage.p->num_cpu; cpu++) {
ptp_t *ptp = (ptp_t *)CPU_L1_TABLE(cpu) + (vaddr >> 20);
*ptp = 0;
}
}
/*
* Map [paddr, paddr+size) with ARM specific attributes in flags.
* If vaddr is ~0, we assign the address, otherwise, the mapping
* will be made at the specified virtual address.
*/
uintptr_t
arm_32_map(uintptr_t vaddr, paddr32_t paddr, size_t size, int flags)
{
static uintptr_t next_addr = ARM_STARTUP_BASE;
paddr32_t off = paddr & PGMASK;
int cpu;
if (!(shdr->flags1 & STARTUP_HDR_FLAGS1_VIRTUAL)) {
return paddr;
}
paddr &= ~PGMASK;
size = ROUNDPG(size + off);
if (vaddr == ~(uintptr_t)0) {
vaddr = next_addr;
next_addr += size;
}
paddr = set_prot(paddr, flags);
for (cpu = 0; cpu < lsp.syspage.p->num_cpu; cpu++) {
size_t sz = size;
uintptr_t va = vaddr;
paddr32_t pa = paddr;
ptp_t *ptp = (ptp_t *)CPU_L1_TABLE(cpu) + ((va >> 20) & ~3);
while (sz) {
int i;
pte_t *pte = (pte_t *)(*ptp & ~PGMASK); // point at start of table
if ((*ptp & ARM_PTP_VALID) == 0) {
/*
* Need to allocate a page table
*/
pte = (pte_t *)calloc_ram(__PAGESIZE, __PAGESIZE);
map_ptbl((uintptr_t)pte, va); // puts four in place at a time
}
pte += (va >> 12) & (ARM_L2_SIZE-1); // start at right slot in table
for (i = (va >> 12) & (ARM_L2_SIZE-1); sz && i < ARM_L2_SIZE; i++) {
*pte++ = pa;
pa += __PAGESIZE;
va += __PAGESIZE;
sz -= __PAGESIZE;
}
ptp += 4; // move to next 4MB set
}
}
return vaddr + off;
}
void
arm_32_map_cpu(int cpu, uintptr_t vaddr, paddr32_t paddr, int flags)
{
ptp_t *ptp = (ptp_t *)CPU_L1_TABLE(cpu) + ((vaddr >> 20) & ~3);
pte_t *pte = (pte_t *)(*ptp & ~PGMASK);
if ((*ptp & ARM_PTP_VALID) == 0) {
/*
* Need to allocate a page table
*/
pte = (pte_t *)calloc_ram(__PAGESIZE, __PAGESIZE);
map_ptbl_cpu(cpu, (uintptr_t)pte, vaddr);
}
pte += (vaddr >> 12) & (ARM_L2_SIZE-1);
*pte = set_prot(paddr, flags);
}
uintptr_t
arm_32_elf_vaddr_to_paddr(uintptr_t vaddr) {
ptp_t *ptp;
pte_t *pte;
ptp = (ptp_t *)CPU_L1_TABLE(0) + (vaddr >> 20);
if ((*ptp & ARM_PTP_VALID) == (ARM_PTP_SC & ARM_PTP_VALID)) {
return (*ptp & ~ARM_SCMASK) + (vaddr & ARM_SCMASK);
} else {
pte = (pte_t *)(*ptp & ~PGMASK);
pte += (vaddr >> 12) & (ARM_L2_SIZE-1);
return (*pte & ~PGMASK) + (vaddr & PGMASK);
}
};
/*
* Map [paddr, paddr+size) with ARM specific attributes in flags.
* If vaddr is ~0, we assign the address, otherwise, the mapping
* will be made at the specified virtual address.
*/
uintptr_t
arm_map(uintptr_t vaddr, paddr_t paddr, size_t size, int flags)
{
#if (_PADDR_BITS-0) == 64
// Use the LPAE version if enabled in the 64-bit build
if (paddr_bits != 32) {
return arm_lpae_map(vaddr, paddr, size, flags);
}
#endif
return arm_32_map(vaddr, (paddr32_t)paddr, size, flags);
}
/*
* Map a page in a cpu-specific page table to allow the same virtual
* address to map different physical pages on each cpu.
*/
void
arm_map_cpu(int cpu, uintptr_t vaddr, paddr_t paddr, int flags)
{
#if (_PADDR_BITS-0) == 64
// Use the LPAE version if enabled in the 64-bit build
if (paddr_bits != 32) {
arm_lpae_map_cpu(cpu, vaddr, paddr, flags);
return;
}
#endif
arm_32_map_cpu(cpu, vaddr, (paddr32_t)paddr, flags);
}
paddr_t
elf_vaddr_to_paddr(uintptr_t vaddr) {
#if (_PADDR_BITS-0) == 64
// Use the LPAE version if enabled in the 64-bit build
if (paddr_bits != 32) {
return arm_lpae_elf_vaddr_to_paddr(vaddr);
}
#endif
return arm_32_elf_vaddr_to_paddr(vaddr);
}

98
src/hardware/startup/lib/arm/arm_pte.c Обычный файл
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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
/*
* The following pointer can be set by a board specific startup program
* to override the value specified by the armv_chip for the CPU
*/
const struct armv_pte *armv_pte;
int arm_v6_mmu;
void
arm_pte_setup()
{
const struct armv_pte *pte;
struct arm_cpu_entry *cpu = lsp.cpu.arm_cpu.p;
if ((pte = armv_pte) == 0) {
if (armv_chip_detect() == 0) {
crash("Unsupported CPUID");
}
if (armv_chip->pte == 0) {
crash("No pte descriptors for %s", armv_chip->name);
}
/*
* Check if -w: overrides page table entries
*/
switch (arm_altpte) {
case 0: // No explicit -w options specified
pte = armv_chip->pte;
break;
case 'a': pte = armv_chip->pte_wa;
break;
case 'b': pte = armv_chip->pte_wb;
break;
case 't': pte = armv_chip->pte_wt;
break;
default: pte = 0;
break;
}
if (pte == 0) {
/*
* Back to default if requested option is not implemented
*/
if (debug_flag) {
kprintf("WARNING: ignoring unsupported -w pte option\n");
}
pte = armv_chip->pte;
}
armv_pte = pte;
}
/*
* Set the arm_cpu fields
*/
cpu->upte_ro = pte->upte_ro;
cpu->upte_rw = pte->upte_rw;
cpu->kpte_ro = pte->kpte_ro;
cpu->kpte_rw = pte->kpte_rw;
cpu->mask_nc = pte->mask_nc;
cpu->ttb_attr = armv_chip->ttb_attr;
cpu->pte_attr = armv_chip->pte_attr;
if (armv_chip->mmu_cr_set & ARM_MMU_CR_XP) {
arm_v6_mmu = 1;
}
}

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2009, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
/*
* Flush entire D-cache and drain write buffer
*/
.text
.align 2
.globl arm_v7_dcache_flush
arm_v7_dcache_flush:
stmfd r13!, {r0-r5, r7, r9-r12, r14}
mrc p15, 1, r0, c0, c0, 1
ands r3, r0, #0x7000000
mov r3, r3, lsr #23
beq finished
mov r10, #0
loop1:
add r2, r10, r10, lsr #1
mov r1, r0, lsr r2
and r1, r1, #7
cmp r1, #2
blt skip
mcr p15, 2, r10, c0, c0, 0
isb
mrc p15, 1, r1, c0, c0, 0
and r2, r1, #7
add r2, r2, #4
ldr r4, =0x3ff
ands r4, r4, r1, lsr #3
clz r5, r4
ldr r7, =0x7fff
ands r7, r7, r1, lsr #13
loop2:
mov r9, r4
loop3:
orr r11, r10, r9, lsl r5
orr r11, r11, r7, lsl r2
mcr p15, 0, r11, c7, c14, 2
subs r9, r9, #1
bge loop3
subs r7, r7, #1
bge loop2
skip:
add r10, r10, #2
cmp r3, r10
bgt loop1
finished:
mov r10, #0
mcr p15, 2, r10, c0, c0, 0
isb
ldmfd r13!, {r0-r5, r7, r9-r12, pc}

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2013 QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
.text
.align 2
.global arm_v7_icache_invalidate
/* Invalidate i-Cache */
arm_v7_icache_invalidate:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0
dsb
isb
mov pc, lr

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_1020 = {
0, // use CP15 cache type register for configuration
&cache_1020_d,
0, // use CP15 cache type register for configuration
&cache_1020_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_1136 = {
0, // use CP15 cache type register for configuration
&cache_1136_d,
0, // use CP15 cache type register for configuration
&cache_1136_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
static const struct arm_cache_config arm720_cache_config = {
CACHE_FLAG_UNIFIED|CACHE_FLAG_VIRTUAL, // flags
16, // line_size
512 // num_lines
};
const struct armv_cache armv_cache_720 = {
&arm720_cache_config, // no cache type register - use static values
&cache_720,
0, // no Icache - use unified cache config
0 // no Icache - use unified cache callouts
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_920 = {
0, // use CP15 cache type register for configuration
&cache_920_d,
0, // use CP15 cache type register for configuration
&cache_920_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_925 = {
0, // use CP15 cache type register for configuration
&cache_925_d,
0, // use CP15 cache type register for configuration
&cache_925_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_926 = {
0, // use CP15 cache type register for configuration
&cache_926_d,
0, // use CP15 cache type register for configuration
&cache_926_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2011, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_a15 = {
0, // use CP15 cache type register for configuration
&cache_a15_d,
0, // use CP15 cache type register for configuration
&cache_a15_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_a7 = {
0, // use CP15 cache type register for configuration
&cache_a7_d,
0, // use CP15 cache type register for configuration
&cache_a7_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_a8 = {
0, // use CP15 cache type register for configuration
&cache_a8_d,
0, // use CP15 cache type register for configuration
&cache_a8_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2009, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_a9mp = {
0, // use CP15 cache type register for configuration
&cache_a9mp_d,
0, // use CP15 cache type register for configuration
&cache_a9mp_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2009, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_a9up = {
0, // use CP15 cache type register for configuration
&cache_a9up_d,
0, // use CP15 cache type register for configuration
&cache_a9up_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_mp11 = {
0, // use CP15 cache type register for configuration
&cache_mp11_d,
0, // use CP15 cache type register for configuration
&cache_mp11_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct arm_cache_config sa1100_dcache_config = {
CACHE_FLAG_DATA|CACHE_FLAG_VIRTUAL|CACHE_FLAG_WRITEBACK,
32,
256
};
const struct arm_cache_config sa1100_icache_config = {
CACHE_FLAG_INSTR|CACHE_FLAG_VIRTUAL,
32,
512
};
const struct armv_cache armv_cache_sa1100 = {
&sa1100_dcache_config, // no cache type register - use static values
&cache_sa_d,
&sa1100_icache_config, // no cache type register - use static values
&cache_sa_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2009, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_sheeva_v6 = {
0, // use CP15 cache type register for configuration
&cache_sheeva_d_v6,
0, // use CP15 cache type register for configuration
&cache_sheeva_i_v6
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2009, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_sheeva_v7 = {
0, // use CP15 cache type register for configuration
&cache_sheeva_d_v7,
0, // use CP15 cache type register for configuration
&cache_sheeva_i_v7
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_xsc3 = {
0, // use CP15 cache type register for configuration
&cache_xsc3_d,
0, // use CP15 cache type register for configuration
&cache_xsc3_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_cache armv_cache_xscale = {
0, // use CP15 cache type register for configuration
&cache_xscale_d,
0, // use CP15 cache type register for configuration
&cache_xscale_i
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_1020 = {
.cpuid = 0xa200,
.name = "arm1020",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_1020,
.power = &power_cp15_wfi,
.flush = &page_flush_1020,
.deferred = &page_flush_deferred_1020,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wt = &armv_pte_v4wt,
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_1022 = {
.cpuid = 0xa220,
.name = "arm1022",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_1020,
.power = &power_cp15_wfi,
.flush = &page_flush_1020,
.deferred = &page_flush_deferred_1020,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wt = &armv_pte_v4wt,
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_1136 = {
.cpuid = 0xb360,
.name = "arm1136",
.mmu_cr_set = ARM_MMU_CR_XP|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = ARM_MMU_CR_R|ARM_MMU_CR_S,
.cycles = 2,
.cache = &armv_cache_1136,
.power = 0,
.flush = &page_flush_1136,
.deferred = &page_flush_deferred_1136,
.pte = &armv_pte_v6wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v6wb,
.pte_wt = &armv_pte_v6wt,
.setup = armv_setup_1136,
.ttb_attr = ARM_TTBR_RGN_WT,
.pte_attr = ARM_PTE_V6_SP_XN|ARM_PTE_WT,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_1176 = {
.cpuid = 0xb760,
.name = "arm1176",
.mmu_cr_set = ARM_MMU_CR_XP|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = ARM_MMU_CR_R|ARM_MMU_CR_S,
.cycles = 2,
.cache = &armv_cache_1136,
.power = 0,
.flush = &page_flush_1136,
.deferred = &page_flush_deferred_1136,
.pte = &armv_pte_v6wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v6wb,
.pte_wt = &armv_pte_v6wt,
.setup = armv_setup_1136,
.ttb_attr = ARM_TTBR_RGN_WT,
.pte_attr = ARM_PTE_V6_SP_XN|ARM_PTE_WT,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_ixp1200 = {
.cpuid = 0xc120,
.name = "ixp1200",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I,
.mmu_cr_clr = 0,
.cycles = 3,
.cache = &armv_cache_sa1100,
.power = 0, // not supported by core
.flush = &page_flush_sa,
.deferred = &page_flush_deferred_sa,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wt = 0, // not supported by core
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_ixp23xx = {
.cpuid = 0x6200,
.name = "ixp23xx",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_L2,
.mmu_cr_clr = ARM_MMU_CR_Z, // cleared due to chip errata
.cycles = 2,
.cache = &armv_cache_xsc3,
.power = 0,
.flush = &page_flush_xsc3,
.deferred = &page_flush_deferred_xsc3,
.pte = &armv_pte_xsc3,
.pte_wa = 0, // not supported see armv_pte_ixp2xxx.c
.pte_wb = &armv_pte_xsc3,
.pte_wt = 0, // not supported see armv_pte_ixp2xxx.c
.setup = armv_setup_xscale,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_ixp2400 = {
.cpuid = 0x4190,
.name = "ixp2400",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_xscale,
.power = &power_xscale,
.flush = &page_flush_xscale,
.deferred = &page_flush_deferred_xscale,
.pte = &armv_pte_ixp2xxx,
.pte_wa = &armv_pte_ixp2xxx,
.pte_wb = 0, // not supported see armv_pte_ixp2xxx.c
.pte_wt = 0, // not supported see armv_pte_ixp2xxx.c
.setup = armv_setup_xscale,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_ixp2800 = {
.cpuid = 0x41a0,
.name = "ixp2800",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_xscale,
.power = &power_xscale,
.flush = &page_flush_xscale,
.deferred = &page_flush_deferred_xscale,
.pte = &armv_pte_ixp2xxx,
.pte_wa = &armv_pte_ixp2xxx,
.pte_wb = 0, // not supported see armv_pte_ixp2xxx.c
.pte_wt = 0, // not supported see armv_pte_ixp2xxx.c
.setup = armv_setup_xscale,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_ixp425 = {
.cpuid = 0x41c0,
.name = "ixp425",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_xscale,
.power = &power_xscale,
.flush = &page_flush_xscale,
.deferred = &page_flush_deferred_xscale,
.pte = &armv_pte_v5wa,
.pte_wa = &armv_pte_v5wa,
.pte_wb = &armv_pte_v5wb,
.pte_wt = &armv_pte_v5wt,
.setup = armv_setup_xscale,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_ixp465 = {
.cpuid = 0x4200,
.name = "ixp465",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_xscale,
.power = &power_xscale,
.flush = &page_flush_xscale,
.deferred = &page_flush_deferred_xscale,
.pte = &armv_pte_v5wa,
.pte_wa = &armv_pte_v5wa,
.pte_wb = &armv_pte_v5wb,
.pte_wt = &armv_pte_v5wt,
.setup = armv_setup_xscale,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_720 = {
.cpuid = 0x7200,
.name = "arm720",
.mmu_cr_set = ARM_MMU_CR_S,
.mmu_cr_clr = 0,
.cycles = 0,
.cache = &armv_cache_720,
.power = 0,
.flush = &page_flush_720,
.deferred = &page_flush_deferred_720,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wt = 0,
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_80200 = {
.cpuid = 0x2000,
.name = "i80200",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_Z,
.mmu_cr_clr = 0,
.cycles = 2,
.cache = &armv_cache_xscale,
.power = &power_xscale,
.flush = &page_flush_xscale,
.deferred = &page_flush_deferred_xscale,
.pte = &armv_pte_v5wb,
.pte_wa = &armv_pte_v5wa,
.pte_wb = &armv_pte_v5wb,
.pte_wt = &armv_pte_v5wt,
.setup = armv_setup_xscale,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_920 = {
.cpuid = 0x9200,
.name = "arm920",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_nF|ARM_MMU_CR_iA,
.mmu_cr_clr = 0,
.cycles = 4,
.cache = &armv_cache_920,
.power = &power_cp15_wfi,
.flush = &page_flush_920,
.deferred = &page_flush_deferred_920,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wt = &armv_pte_v4wt,
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_922 = {
.cpuid = 0x9200,
.name = "arm922",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I|ARM_MMU_CR_nF|ARM_MMU_CR_iA,
.mmu_cr_clr = 0,
.cycles = 4,
.cache = &armv_cache_920,
.power = &power_cp15_wfi,
.flush = &page_flush_920,
.deferred = &page_flush_deferred_920,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wa = &armv_pte_v4wt,
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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/*
* (c) 2010, SWD Embedded Systems Limited, http://www.kpda.ru
*/
/*
* $QNXLicenseC:
* Copyright 2008, QNX Software Systems.
*
* Licensed under the Apache License, Version 2.0 (the "License"). You
* may not reproduce, modify or distribute this software except in
* compliance with the License. You may obtain a copy of the License
* at: http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
*
* This file may contain contributions from others, either as
* contributors under the License or as licensors under other terms.
* Please review this entire file for other proprietary rights or license
* notices, as well as the QNX Development Suite License Guide at
* http://licensing.qnx.com/license-guide/ for other information.
* $
*/
#include "startup.h"
const struct armv_chip armv_chip_925 = {
.cpuid = 0x9250,
.name = "arm925",
.mmu_cr_set = ARM_MMU_CR_S|ARM_MMU_CR_I,
.mmu_cr_clr = 0,
.cycles = 4,
.cache = &armv_cache_925,
.power = &power_cp15_wfi,
.flush = &page_flush_925,
.deferred = &page_flush_deferred_925,
.pte = &armv_pte_v4wb,
.pte_wa = 0, // not supported by core
.pte_wb = &armv_pte_v4wb,
.pte_wt = &armv_pte_v4wt,
.setup = 0,
.ttb_attr = 0,
.pte_attr = 0,
};

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